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1.发明授权Hardware clipping device which compares objects with boundaries via use of absolute values 失效通过使用绝对值将对象与边界进行比较的硬件裁剪装置
公开(公告)号：US5982380A
公开(公告)日：1999-11-09
申请号：US929438
申请日：1997-09-16
CPC分类号： G06T15/30
摘要： It is judged that a vertex exists within a view volume when values stored in registers (231 to 236) are all "1". In other words, whether the vertex exists within or beyond the view volume can be judged by whether the values stored in the registers (231 to 236) are all "1" or not. To meet this requirement, a clip code generation/judgment unit (20) comprises a 6-input AND gate (24) which obtains a logical product of the values stored in the registers (231 to 236) to output a judgment signal (M1). With this configuration, a first step for clipping, i.e., the judgment on whether a primitive exists within or beyond a view volume is implemented in hardware, and thereby the operating speed is improved.
摘要翻译： 在存储在寄存器（231〜236）中的值全部为“1”的情况下，判断为在视野内存在顶点。 换句话说，可以通过存储在寄存器（231至236）中的值是否全部为“1”来判断顶点是否存在于视图体中或超出视图体积。 为了满足该要求，剪辑码生成/判断单元（20）包括6输入与门（24），其获得存储在寄存器（231至236）中的值的逻辑积，以输出判断信号（M1） 。 利用这种配置，在硬件中实现用于削波的第一步骤，即在视图体中或超过视图体积中是否存在基元的判断，从而提高了操作速度。
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公开(公告)号：US06442627B1
公开(公告)日：2002-08-27
申请号：US09453547
申请日：1999-12-03
申请人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
发明人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
IPC分类号： G06F300
摘要： An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units. A transfer mode setting unit sets a transfer mode identifying which at least one of the plurality of processing units is to transfer data on an arithmetic result, and sequentially furnishes a read enable signal to at least one of the plurality of processing units so as to read out the data from the intermediate buffer of at least one of the plurality of processing units.
摘要翻译： 输出FIFO数据传送控制装置可以包括包括一个整数处理单元或IPU以及多个浮点处理单元或FPU的几何运算核心。 每个处理单元包括用于存储关于算术结果的数据的中间缓冲器或数据输出缓冲器。 当发出从多个处理单元中的至少一个处理单元到一个输出FIFO的数据传送指令时，写入/读出指针生成单元产生一个写入指针，该指针识别与该指令相关联的算术结果的数据为 被存储在多个处理单元中的至少一个处理单元的中间缓冲器中。 写/读指针生成单元还生成识别要从多个处理单元中的至少一个的中间缓冲器读出数据的特定位置的读指针。 传送模式设置单元设置传送模式，其识别多个处理单元中的至少一个处理单元是在算术结果上传送数据，并且将读取使能信号顺序地提供给多个处理单元中的至少一个，以便读取 从多个处理单元中的至少一个的中间缓冲器输出数据。
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3.发明授权Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel 有权能够并行执行输入/输出和高速几何计算处理的几何处理器公开(公告)号：US06603481B1
公开(公告)日：2003-08-05
申请号：US09294002
申请日：1999-04-19
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.
摘要翻译： 几何处理器包括分别连接到主机处理器和渲染处理器的相互独立的第一和第二外部接口端口以及处理通过第一外部接口端口从主机处理器应用的几何计算的几何计算核心。 几何计算核心包括多个SIMD型浮点计算单元，浮点计算单元，整数计算单元，响应于来自主处理器的控制多个浮点计算单元的指令的控制器，浮点 功率计算单元和用于处理来自主处理器的数据的整数计算单元，以及输出控制器，其通过第二外部接口端口将处理后的数据输出到渲染处理器。
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公开(公告)号：US06480873B1
公开(公告)日：2002-11-12
申请号：US09478004
申请日：2000-01-05
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Robert Streitenberger , Keijiro Yoshimatsu , Hiroyasu Negishi
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Robert Streitenberger , Keijiro Yoshimatsu , Hiroyasu Negishi
IPC分类号： G06F738
CPC分类号： G06F7/556
摘要： A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e., computes 2Z where Z is the selected multiplication bit string, and furnishes the computed base-2 exponential value as the power operation-result XY.
摘要翻译： 电力操作装置包括位操作单元或者根据输入的指数位串Y从对数运算单元对对数基本位串执行位移操作，并将移位的对数基本位串提供为乘法位串。 指数检查单元检查输入指数位串Y是否是基数2的第i个幂，其中i是整数，如果是，则提供选择信号以从位操作单元直接选择乘法位串 。 乘法比特串选择单元当从指数检查单元接收到选择信号时，选择并提供乘法比特串。 相反，乘法比特串选择单元否则从乘数中选择并提供另一乘法比特串。 指数运算单元从乘法位串选择单元对所选择的乘法比特串执行基2指数运算，即计算2Z，其中Z是所选乘法位串，并将计算出的基2指数值作为幂 操作结果XY。
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公开(公告)号：US5974436A
公开(公告)日：1999-10-26
申请号：US954586
申请日：1997-10-20
CPC分类号： G06F7/556 , G06F7/5525 , G06F2207/5561
摘要： An execution processor that can carry out power calculation at high speed includes a base data register, an exponent data register, a multiplier, a multiplication input selector for selecting an input to the multiplier, first and second registers for storing a calculation result of the multiplier, a square root calculation unit, a square root calculation input selector for selecting an input to the square root calculation unit, a third register for storing a calculation result of the square root calculation unit, and a power calculation controller. The power calculation controller checks the integer region of the exponent data register for each bit while providing input/output control of the multiplication input selector, the first register, and the second register, and checks the decimal fraction region of the exponent data register for each bit to provide input/output control of the square root calculation input selector, the multiplication input selector, the first register, the second register, and the third register.
摘要翻译： 可以高速执行功率计算的执行处理器包括基本数据寄存器，指数数据寄存器，乘法器，用于选择到乘法器的输入的乘法输入选择器，用于存储乘法器的计算结果的第一和第二寄存器 平方根计算单元，用于选择对平方根计算单元的输入的平方根计算输入选择器，存储平方根计算单元的计算结果的第三寄存器和功率计算控制器。 功率计算控制器为每个位检查指数数据寄存器的整数区域，同时提供乘法输入选择器，第一寄存器和第二寄存器的输入/输出控制，并且为每个位检查指数数据寄存器的小数部分区域 位提供平方根计算输入选择器，乘法输入选择器，第一寄存器，第二寄存器和第三寄存器的输入/输出控制。
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6.发明授权Geometrical operation apparatus for performing high speed calculations in a three-dimensional computer graphic display system 失效用于在三维计算机图形显示系统中执行高速计算的几何运算装置
公开(公告)号：US6005590A
公开(公告)日：1999-12-21
申请号：US743178
申请日：1996-11-05
CPC分类号： G06T1/20
摘要： The apparatus comprises an input memory 102 for storing data necessary for geometrical operations, such as coordinate transformation, luminance calculation, and clipping operation of graphics; a global bus connected to the input memory; a plurality of floating process memories connected to the global bus, for receiving data necessary for geometrical operations; a sequencer for transmitting data necessary for geometrical operations, stored in the input memory, to the plurality of floating process memories; and a plurality of floating processing units each connected to a respective one of the plurality of floating process memories, for independently executing geometrical operations, using data transmitted from the floating process memories.
摘要翻译： 该装置包括用于存储几何运算所必需的数据的输入存储器102，例如坐标变换，亮度计算和图形的剪切操作; 连接到输入存储器的全局总线; 连接到全局总线的多个浮动处理存储器，用于接收几何操作所需的数据; 定序器，用于将存储在输入存储器中的几何运算所需的数据发送到多个浮动处理存储器; 以及多个浮动处理单元，每个浮动处理单元都连接到多个浮动处理存储器中的相应一个浮动处理存储器，用于使用从浮动处理存储器发送的数据来独立地执行几何操作。
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公开(公告)号：US20060200631A1
公开(公告)日：2006-09-07
申请号：US11068862
申请日：2005-03-02
申请人： Seiji Seki , Toshihisa Kamemaru , Hiroyasu Negishi , Junko Kobara
发明人： Seiji Seki , Toshihisa Kamemaru , Hiroyasu Negishi , Junko Kobara
IPC分类号： G06F13/28
CPC分类号： G06F12/0862
摘要： The present invention aims to prefetch data which is stored in a cache memory and whose probability of access is high by replacing data whose probability of access is low. On discriminating a cache miss of target data which is used for an operation process performed by an operation processing unit, a cache hit discriminating unit obtains the target data from a main memory. Further, when the cache hit discriminating unit discriminates a cache hit, an invalid data discriminating unit discriminates a cache line including the target data is the same as the one including data which has been used for the previous operation process. Then, when the invalid data discriminating unit discriminates the cache line including the target data is different from the cache line including the data used for the previous operation process, a prefetch controlling unit prefetches the data by replacing data stored in the main memory with the cache line including the data used for the previous operation process.
摘要翻译： 本发明旨在通过替换访问概率低的数据来预取存储在高速缓存存储器中并且其访问概率高的数据。 在识别用于由操作处理单元执行的操作处理的目标数据的高速缓存未命中时，高速缓存命中鉴别单元从主存储器获得目标数据。 此外，当高速缓存命中鉴别单元识别高速缓存命中时，无效数据鉴别单元鉴别包括目标数据的高速缓存行与包括用于先前操作处理的数据的高速缓存行相同。 然后，当无效数据识别单元识别包括目标数据的高速缓存行不同于包括用于先前操作处理的数据的高速缓存行时，预取控制单元通过用高速缓存代替存储在主存储器中的数据来预取数据 行包括用于先前操作过程的数据。
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公开(公告)号：US20100271382A1
公开(公告)日：2010-10-28
申请号：US12810192
申请日：2008-01-15
申请人： Yoshiyuki Kato , Akira Torii , Hiroyasu Negishi , Ryohei Ishida , Masaki Hamada
发明人： Yoshiyuki Kato , Akira Torii , Hiroyasu Negishi , Ryohei Ishida , Masaki Hamada
CPC分类号： G06T11/203 , G09G5/28
摘要： A distance information generating unit 4 for rasterizing minute line segments divided by a curved line dividing unit 2 through a combination of straight line cells and corner cells to generate distance information corresponding to a pixel 12 of a display and an edge rasterizing unit 7 for rasterizing edge information about the minute line segments divided by the curved line dividing unit 2 are disposed, and a mapping unit 10 determines whether the pixel 12 is located inside or outside by using the edge information rasterized by the edge rasterizing unit 7, and maps the distance information generated by the distance information generating unit 4 onto the antialiasing intensity 11 of a component 13 included in the pixel 12 according to the results of the inside or outside determination.
摘要翻译： 距离信息生成单元4，用于通过直线单元和角点单元的组合对通过曲线划分单元2分割的细线段光栅化，以产生对应于显示器的像素12的距离信息和用于光栅化边缘的边缘光栅化单元7 布置由曲线分割单元2分割的细线段的信息，并且映射单元10通过使用由边缘光栅化单元7光栅化的边缘信息来确定像素12是位于内部还是外部，并将距离信息 根据内部或外部确定的结果，由距离信息生成单元4产生的像素12中包括的分量13的抗混叠强度11。
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公开(公告)号：US08520007B2
公开(公告)日：2013-08-27
申请号：US12810192
申请日：2008-01-15
申请人： Yoshiyuki Kato , Akira Torii , Hiroyasu Negishi , Ryohei Ishida , Masaki Hamada
发明人： Yoshiyuki Kato , Akira Torii , Hiroyasu Negishi , Ryohei Ishida , Masaki Hamada
CPC分类号： G06T11/203 , G09G5/28
摘要： A distance information generating unit 4 for rasterizing minute line segments divided by a curved line dividing unit 2 through a combination of straight line cells and corner cells to generate distance information corresponding to a pixel 12 of a display and an edge rasterizing unit 7 for rasterizing edge information about the minute line segments divided by the curved line dividing unit 2 are disposed, and a mapping unit 10 determines whether the pixel 12 is located inside or outside by using the edge information rasterized by the edge rasterizing unit 7, and maps the distance information generated by the distance information generating unit 4 onto the antialiasing intensity 11 of a component 13 included in the pixel 12 according to the results of the inside or outside determination.
摘要翻译： 距离信息生成单元4，用于通过直线单元和角点单元的组合对通过曲线划分单元2分割的细线段光栅化，以产生对应于显示器的像素12的距离信息和用于光栅化边缘的边缘光栅化单元7 布置由曲线分割单元2分割的细线段的信息，并且映射单元10通过使用由边缘光栅化单元7光栅化的边缘信息来确定像素12是位于内部还是外部，并将距离信息 根据内部或外部确定的结果，由距离信息生成单元4产生的像素12中包括的分量13的抗混叠强度11。
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公开(公告)号：US20140354652A1
公开(公告)日：2014-12-04
申请号：US14373682
申请日：2012-04-27
CPC分类号： G09G5/28 , G06F17/214 , G06T11/203 , G09G5/24
摘要： A character drawing device includes a system memory that stores outline fonts each defining outlines of characters, and an arithmetic processor that generates rectangles on the outline part of a character shown by an outline font read from the above-mentioned storage, adjusts a width of each of the generated rectangles according to the thickness of the character, and sets a degree of transparency to an inside region of the character which is enclosed by each of the rectangles after the adjustment and a degree of transparency to each of the rectangles to draw the character.
摘要翻译： 字符绘制装置包括存储每个定义字符轮廓的轮廓字体的系统存储器，以及在从上述存储器读取的轮廓字体所示的字符的轮廓部分上生成矩形的运算处理器， 根据字符的厚度生成矩形，并将透明度设置为在调整之后被每个矩形包围的字符的内部区域，并且将每个矩形的透明度设置为绘制字符 。
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