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    Current mode logic-CMOS converter
    3.
    发明授权
    Current mode logic-CMOS converter 有权
    电流模式逻辑CMOS转换器

    公开(公告)号：US07405600B2

    公开(公告)日：2008-07-29

    申请号：US11831348

    申请日：2007-07-31

    申请人： Yu Sin Kim ,  Jeong Ho Moon ,  Moo Il Jeong ,  Chang Seok Lee ,  Chang Soo Yang ,  Sang Gyu Park ,  Kwang Du Lee

    发明人： Yu Sin Kim ,  Jeong Ho Moon ,  Moo Il Jeong ,  Chang Seok Lee ,  Chang Soo Yang ,  Sang Gyu Park ,  Kwang Du Lee

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018514

    摘要： A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned on/off by the constant voltage applied from the voltage control unit; and a second switching unit that is connected to the input stage and is turned on/off by a signal applied from the input stage.

    摘要翻译： 电流模式逻辑（CML）-CMOS转换器包括通过从外部接收输入电压而被接通/断开的输入级; 输出恒定电压的电压控制单元; 第一开关单元，其连接到所述输入级和所述电压控制单元，并且通过从所述电压控制单元施加的恒定电压来接通/断开; 以及第二开关单元，其连接到所述输入级，并且通过从所述输入级施加的信号导通/截止。

    Method for compensating performance degradation of RFIC using EM simulation
    4.
    发明授权
    Method for compensating performance degradation of RFIC using EM simulation 有权
    使用EM模拟来补偿RFIC性能下降的方法

    公开(公告)号：US07954079B2

    公开(公告)日：2011-05-31

    申请号：US11943211

    申请日：2007-11-20

    申请人： Yu Sin Kim ,  Chang Seok Lee ,  Chang Soo Yang ,  Kwang Du Lee ,  Hak Sun Kim

    发明人： Yu Sin Kim ,  Chang Seok Lee ,  Chang Soo Yang ,  Kwang Du Lee ,  Hak Sun Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5036

    摘要： Provided is a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an EM simulation. The method includes the steps of: (a) extracting the design specifications of the RFIC so as design and simulate a circuit; (b) designing the layout of the designed and simulated circuit, and extracting layout parameters by using the designed layout; (c) simplifying the layout and carrying out the EM simulation to extract performance parameters; (d) carrying out a circuit simulation by using the extracted layout parameters and performance parameters, and judging whether the results of the circuit simulation satisfy the design specifications of the RFIC or not; (e) when it is judged that the results of the circuit simulation satisfy the design specifications of the RFIC, performing a circuit manufacturing process; and (f) when it is not judged that the results of the circuit simulation satisfy the design specifications of the RFIC, partially removing the layout, and carrying out the EM simulation, thereby analyzing and compensating a performance degradation region.

    摘要翻译： 提供了一种使用EM模拟来补偿射频集成电路（RFIC）的性能劣化的方法。 该方法包括以下步骤：（a）提取RFIC的设计规范，以设计和模拟电路; （b）设计和仿真电路的布局设计，并通过设计布局提取布局参数; （c）简化布局并执行EM仿真以提取性能参数; （d）使用提取的布局参数和性能参数进行电路仿真，判断电路仿真结果是否满足RFIC的设计规范; （e）当判断电路仿真的结果满足RFIC的设计规范时，执行电路制造过程; 和（f）当不判断电路仿真的结果满足RFIC的设计规范时，部分地去除布局并进行EM仿真，从而分析和补偿性能退化区域。

    CURRENT MODE LOGIC-CMOS CONVERTER
    5.
    发明申请
    CURRENT MODE LOGIC-CMOS CONVERTER 有权
    电流模式逻辑 - CMOS转换器

    公开(公告)号：US20080036496A1

    公开(公告)日：2008-02-14

    申请号：US11831348

    申请日：2007-07-31

    申请人： Yu Sin KIM ,  Jeong Ho Moon ,  Moo II Jeong ,  Chang Seok Lee ,  Chang Soo Yang ,  Sang Gyu Park ,  Kwang Du Lee

    发明人： Yu Sin KIM ,  Jeong Ho Moon ,  Moo II Jeong ,  Chang Seok Lee ,  Chang Soo Yang ,  Sang Gyu Park ,  Kwang Du Lee

    IPC分类号： H03K19/0175 ,  G05F1/44 ,  H03K19/20

    CPC分类号： H03K19/018514

    摘要： A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned on/off by the constant voltage applied from the voltage control unit; and a second switching unit that is connected to the input stage and is turned on/off by a signal applied from the input stage.

    摘要翻译： 电流模式逻辑（CML）-CMOS转换器包括通过从外部接收输入电压而被接通/断开的输入级; 输出恒定电压的电压控制单元; 第一开关单元，其连接到所述输入级和所述电压控制单元，并且通过从所述电压控制单元施加的恒定电压来接通/断开; 以及第二开关单元，其连接到所述输入级，并且通过从所述输入级施加的信号导通/截止。

    ULTRA-WIDE BAND PULSE SIGNAL GENERATOR
    6.
    发明申请
    ULTRA-WIDE BAND PULSE SIGNAL GENERATOR 审中-公开
    超宽带脉冲信号发生器

    公开(公告)号：US20090072876A1

    公开(公告)日：2009-03-19

    申请号：US12210127

    申请日：2008-09-12

    申请人： Yu Sin KIM ,  Chang Seok Lee ,  Kwang Du Lee ,  Chang Soo Yang

    发明人： Yu Sin KIM ,  Chang Seok Lee ,  Kwang Du Lee ,  Chang Soo Yang

    IPC分类号： H03K3/00

    CPC分类号： H03K5/12 ,  H03K5/159 ,  H04B1/7174

    摘要： There is provided an ultra-wide band pulse signal generator that can vary a waveform and bandwidth of a pulse signal by delaying transmitted data according to a clock signal without using a delay line to generate the pulse signal. An ultra-wide band pulse signal generator according to an aspect of the invention may include: a signal generating unit sequentially delaying transmitted data according to a predetermined clock signal to generate a plurality of pulse signals; an amplification unit amplifying the plurality of pulse signals from the signal generating unit according to predetermined amplification ratios; and a combination unit combining the plurality of pulse signals amplified by the amplification unit.

    摘要翻译： 提供了一种超宽带脉冲信号发生器，其可以通过根据时钟信号延迟发送的数据而不使用延迟线来产生脉冲信号来改变脉冲信号的波形和带宽。 根据本发明的一个方面的超宽带脉冲信号发生器可以包括：信号发生单元，根据预定的时钟信号顺序地延迟所发送的数据，以产生多个脉冲信号; 放大单元，根据预定的放大率，放大来自信号发生单元的多个脉冲信号; 以及组合由放大单元放大的多个脉冲信号的组合单元。

    METHOD FOR COMPENSATING PERFORMANCE DEGRADATION OF RFIC USING EM SIMULATION
    7.
    发明申请
    METHOD FOR COMPENSATING PERFORMANCE DEGRADATION OF RFIC USING EM SIMULATION 有权
    使用EM模拟来补偿RFIC性能降低的方法

    公开(公告)号：US20080134112A1

    公开(公告)日：2008-06-05

    申请号：US11943211

    申请日：2007-11-20

    申请人： Yu Sin Kim ,  Chang Seok Lee ,  Chang Soo Yang ,  Kwang Du Lee ,  Hak Sun Kim

    发明人： Yu Sin Kim ,  Chang Seok Lee ,  Chang Soo Yang ,  Kwang Du Lee ,  Hak Sun Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5036

    摘要： Provided is a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an EM simulation. The method includes the steps of: (a) extracting the design specifications of the RFIC so as design and simulate a circuit; (b) designing the layout of the designed and simulated circuit, and extracting layout parameters by using the designed layout; (c) simplifying the layout and carrying out the EM simulation to extract performance parameters; (d) carrying out a circuit simulation by using the extracted layout parameters and performance parameters, and judging whether the results of the circuit simulation satisfy the design specifications of the RFIC or not; (e) when it is judged that the results of the circuit simulation satisfy the design specifications of the RFIC, performing a circuit manufacturing process; and (f) when it is not judged that the results of the circuit simulation satisfy the design specifications of the RFIC, partially removing the layout, and carrying out the EM simulation, thereby analyzing and compensating a performance degradation region.

    摘要翻译： 提供了一种使用EM模拟来补偿射频集成电路（RFIC）的性能劣化的方法。 该方法包括以下步骤：（a）提取RFIC的设计规范，以设计和模拟电路; （b）设计和仿真电路的布局设计，并通过设计布局提取布局参数; （c）简化布局并执行EM仿真以提取性能参数; （d）使用提取的布局参数和性能参数进行电路仿真，判断电路仿真结果是否符合RFIC的设计规范; （e）当判断电路仿真的结果满足RFIC的设计规范时，执行电路制造过程; 和（f）当不判断电路仿真的结果满足RFIC的设计规范时，部分地去除布局并进行EM仿真，从而分析和补偿性能退化区域。

    Method and device for updating a database for wireless LAN based positioning
    8.
    发明授权
    Method and device for updating a database for wireless LAN based positioning 有权
    用于更新无线LAN定位的数据库的方法和设备

    公开(公告)号：US09215604B2

    公开(公告)日：2015-12-15

    申请号：US13808328

    申请日：2011-06-28

    申请人： Suk Yon Kang ,  Seung Yoon Baek ,  Hye Min Lee ,  Chang Seok Lee ,  Chae Hwan Cho

    发明人： Suk Yon Kang ,  Seung Yoon Baek ,  Hye Min Lee ,  Chang Seok Lee ,  Chae Hwan Cho

    IPC分类号： H04L1/00 ,  H04W24/02 ,  H04W64/00 ,  G01S5/02 ,  H04W84/12

    CPC分类号： H04W24/02 ,  G01S5/021 ,  G01S5/0252 ,  H04W64/00 ,  H04W84/12

    摘要： An apparatus for updating a database for wireless LAN based positioning includes a database for storing grid cells divided by pCell ID and base station-derived environment information and wireless LAN environment information matched to the grid cells; a grid cell determining unit for determining an information-unmeasured grid cell among the grid cells, the information-unmeasured grid cell being a grid cell that has unmeasured information among parameters of the wireless LAN environment information matched to the grid cells; an unmeasured parameter checking unit for checking an unmeasured parameter in the information-unmeasured grid cell; a radiowave environment estimating unit for generating radiowave environment estimation information by estimating the unmeasured information based on the unmeasured parameter checked; and a database updating unit for reflecting the radiowave environment estimation information in the information-unmeasured grid cell determined.

    摘要翻译： 一种用于更新用于基于无线LAN的定位的数据库的装置包括：用于存储由pCell ID和基站导出的环境信息以及与网格单元匹配的无线LAN环境信息划分的网格单元的数据库; 网格单元确定单元，用于确定网格单元之间的信息未测量网格单元，所述信息未测量网格单元是在与所述网格单元匹配的无线LAN环境信息的参数中具有未测量信息的网格单元; 用于检查信息未测量网格单元中的未测量参数的未测量参数检查单元; 无线电波环境估计单元，用于通过基于所检查的未测量参数估计未测量信息来生成无线电波环境估计信息; 以及数据库更新单元，用于反映所确定的信息未测量网格单元中的无线电波环境估计信息。

    Illumination driving apparatus
    9.
    发明授权
    Illumination driving apparatus 有权
    照明驱动装置

    公开(公告)号：US08779682B2

    公开(公告)日：2014-07-15

    申请号：US13290738

    申请日：2011-11-07

    申请人： Joong Ho Choi ,  Yeun Joong Lee ,  Deuk Hee Park ,  Sang Hyun Cha ,  Chang Seok Lee

    发明人： Joong Ho Choi ,  Yeun Joong Lee ,  Deuk Hee Park ,  Sang Hyun Cha ,  Chang Seok Lee

    IPC分类号： H05B37/02

    CPC分类号： H05B33/0815 ,  H05B33/0845 ,  H05B33/0851

    摘要： A fixture-compatible, dimmable illumination driving apparatus including: a rectifying unit rectifying a phase-controlled waveform of an alternating current (AC) power; a comparing unit comparing an output waveform of the rectifying unit with a first voltage according to a preset reference clock; a reference voltage generating unit generating a reference voltage corresponding to the number of high signals higher than the first voltage among outputs of the comparing unit during one cycle of the output waveform; and a pulse width modulation (PWM) signal generating unit generating a PWM signal from the reference voltage and a feedback voltage.

    摘要翻译： 一种灯具兼容的可调光照明驱动装置，包括：整流单元，对交流（AC）功率的相位控制波形进行整流; 比较单元，根据预设的参考时钟将整流单元的输出波形与第一电压进行比较; 参考电压产生单元，在所述输出波形的一个周期期间，生成与所述比较单元的输出之间高于所述第一电压的高信号的数量相对应的参考电压; 以及脉冲宽度调制（PWM）信号生成单元，从所述基准电压和反馈电压生成PWM信号。

    DRIVING APPARATUS FOR LIGHT EMITTING DIODE
    10.
    发明申请
    DRIVING APPARATUS FOR LIGHT EMITTING DIODE 审中-公开
    用于发光二极管的驱动装置

    公开(公告)号：US20130162154A1

    公开(公告)日：2013-06-27

    申请号：US13440687

    申请日：2012-04-05

    申请人： Yeun Joong LEE ,  Deuk Hee Park ,  Jae Shin Lee ,  Sang Hyun Cha ,  Chang Seok Lee

    发明人： Yeun Joong LEE ,  Deuk Hee Park ,  Jae Shin Lee ,  Sang Hyun Cha ,  Chang Seok Lee

    IPC分类号： H05B37/00

    CPC分类号： H05B33/0824 ,  H05B33/0818 ,  H05B33/0851

    摘要： There is provided a driving apparatus for a light emitting diode (LED) comparing a rectified power voltage level with an LED current to limit current applied to an LED, thereby reducing the amount of heat generated therein. The driving apparatus for an LED includes a detecting unit detecting a voltage level of rectified power; and a driving unit comparing a level of current flowing in an LED unit having at least one LED with detection results from the detecting unit, and limiting current applied to the LED unit to drive the LED unit according to comparison results.

    摘要翻译： 提供了一种用于将整流的电压电平与LED电流进行比较的发光二极管（LED）的驱动装置，以限制施加到LED的电流，从而减少其中产生的热量。 用于LED的驱动装置包括：检测单元，用于检测整流电源的电压电平; 以及驱动单元，比较在具有至少一个LED的LED单元中流动的电流的水平与来自检测单元的检测结果，并且根据比较结果限制施加到LED单元以驱动LED单元。