公开(公告)号：US09082332B2

公开(公告)日：2015-07-14

申请号：US12128372

申请日：2008-05-28

申请人： Yu-Pin Chou ,  Szu-Ping Chen ,  Yu Jen Lin

发明人： Yu-Pin Chou ,  Szu-Ping Chen ,  Yu Jen Lin

IPC分类号： G09G5/02 ,  G09G5/00

CPC分类号： G06T1/60 ,  G09G3/28 ,  G09G3/36 ,  G09G5/005 ,  G09G2310/08 ,  G09G2340/0414 ,  G09G2340/0421

摘要： The invention discloses a mode detection circuit and a method thereof, for detecting an image signal, the image signal includes a horizontal resolution and the vertical resolution. The mode detection circuit includes a measuring unit, a calculation unit, and a decision unit. The measuring unit receives a clock signal and is used to count the clock signal to output a first counting value and the second counting value. The calculation unit is used to perform the calculation with the first counting value and the second counting value and thereby outputting a calculating value, wherein the calculating value outputted by the calculation unit is corresponding to the ratio of the first counting value to the second counting value. The decision unit is used to determine the horizontal resolution or the vertical resolution according to the calculating value.

摘要翻译： 本发明公开了一种模式检测电路及其方法，用于检测图像信号，图像信号包括水平分辨率和垂直分辨率。 模式检测电路包括测量单元，计算单元和判定单元。 测量单元接收时钟信号，并用于对时钟信号进行计数以输出第一计数值和第二计数值。 计算单元用于执行具有第一计数值和第二计数值的计算，从而输出计算值，其中由计算单元输出的计算值对应于第一计数值与第二计数值的比率 。 决策单元用于根据计算值确定水平分辨率或垂直分辨率。

公开(公告)号：US20080007656A1

公开(公告)日：2008-01-10

申请号：US11822392

申请日：2007-07-05

申请人： Jui-Yuan Tsai ,  Szu-Ping Chen ,  Yu-Pin Chou

发明人： Jui-Yuan Tsai ,  Szu-Ping Chen ,  Yu-Pin Chou

IPC分类号： H04N5/06 ,  H04N9/72

CPC分类号： H04N5/08 ,  H04N5/185 ,  H04N9/44

摘要： A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

摘要翻译： 公开了一种同步信号采集装置，其包括晶体管，电阻器，钳位器，模拟多路复用器和比较器。 当在复合HS模式下操作时，在产生同步信号HS之前，本发明使用常规电路在启动时提取复合同步信号，从而允许相关电路产生同步信号HS和钳位信号。 然后，使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。 此时，阻尼器的输出电压由使用者而不是过程设定; 因此，直流电压电平更可控，但由于过程变化或温度变化而不会发生漂移。

公开(公告)号：US08212938B2

公开(公告)日：2012-07-03

申请号：US11822392

申请日：2007-07-05

申请人： Jui-Yuan Tsai ,  Szu-Ping Chen ,  Yu-Pin Chou

发明人： Jui-Yuan Tsai ,  Szu-Ping Chen ,  Yu-Pin Chou

IPC分类号： H04N9/72

CPC分类号： H04N5/08 ,  H04N5/185 ,  H04N9/44

摘要： A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

摘要翻译： 公开了一种同步信号采集装置，其包括晶体管，电阻器，钳位器，模拟多路复用器和比较器。 当在复合HS模式下操作时，在产生同步信号HS之前，本发明使用常规电路在启动时提取复合同步信号，从而允许相关电路产生同步信号HS和钳位信号。 然后，使用模式选择信号来禁用自动钳位模式并将模拟多路复用器切换到强制钳位模式。 此时，阻尼器的输出电压由使用者而不是过程设定; 因此，直流电压电平更可控，但由于过程变化或温度变化而不会发生漂移。

公开(公告)号：US08514206B2

公开(公告)日：2013-08-20

申请号：US12314601

申请日：2008-12-12

申请人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

发明人： Yu-Pin Chou ,  Tzuo-Bo Lin ,  Ming-Syun Wu

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  G09G5/005 ,  G09G2370/12

摘要： A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

公开(公告)号：US20100014621A1

公开(公告)日：2010-01-21

申请号：US12501959

申请日：2009-07-13

申请人： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

发明人： Tzuo-Bo Lin ,  Bing-Juo Chuang ,  Yu-Pin Chou

IPC分类号： H04L7/00

CPC分类号： H04L7/10 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/12 ,  H04L7/046 ,  H04L25/4908

摘要： A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

摘要翻译： 接收机包括 恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。 数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。 还公开了接收机的方法。

公开(公告)号：US20090015722A1

公开(公告)日：2009-01-15

申请号：US12128634

申请日：2008-05-29

申请人： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

发明人： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

IPC分类号： H04N5/44

CPC分类号： H04N5/4401 ,  H04N5/46 ,  H04N5/765 ,  H04N21/42615 ,  H04N21/4305 ,  H04N21/436 ,  H04N21/4363

摘要： The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

摘要翻译： 本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。 信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。 输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子 对应于具有该组共享输入端的第二传输规范。 接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。

公开(公告)号：US20080094145A1

公开(公告)日：2008-04-24

申请号：US11874209

申请日：2007-10-18

申请人： Chi-Kung Kuan ,  Yu-Pin Chou ,  Yi-Teng Chen

发明人： Chi-Kung Kuan ,  Yu-Pin Chou ,  Yi-Teng Chen

IPC分类号： H03L7/087 ,  H03L7/00

CPC分类号： H03L7/087 ,  H03L7/081 ,  H03L7/1976 ,  H03L7/23

摘要： A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

摘要翻译： 提供了包括数字PFD，数字环路滤波器，判决电路，分数N PLL和分频器的锁相环（PLL）。 数字PFD根据输入信号和反馈信号之间的相位误差或频率差产生第一检测信号。 数字环路滤波器根据第一检测信号产生第一控制信号。 决定电路根据第一控制信号产生除数值。 分数N PLL根据除数值和参考信号产生振荡信号。 分频器分频振荡信号产生反馈信号。 分数N PLL包括分数N分频器，用于通过采用相位吞吐装置，根据除数值产生用于跟踪参考信号的分频信号。

公开(公告)号：US07218177B2

公开(公告)日：2007-05-15

申请号：US11160767

申请日：2005-07-07

申请人： Yu-Pin Chou ,  Chia-Liang Chiang

发明人： Yu-Pin Chou ,  Chia-Liang Chiang

IPC分类号： H03L7/00

CPC分类号： H03L7/0891 ,  H03L7/093

摘要： A phase-locked loop includes a phase/frequency detector for generating phase error signal according to a reference signal and an input signal, a charge pump for outputting a voltage signal according to the phase error signal, a voltage-controlled oscillator for outputting an output signal corresponding to the phase error signal according to the voltage signal, an adaptive adjusting unit for outputting a control signal according to the phase error signal, so as to form a nonlinear between the output signal and the phase error signal.

摘要翻译： 锁相环包括用于根据参考信号和输入信号产生相位误差信号的相位/频率检测器，用于根据相位误差信号输出电压信号的电荷泵，用于输出输出的电压控制振荡器 根据电压信号对应于相位误差信号的信号，自适应调整单元，用于根据相位误差信号输出控制信号，以便在输出信号和相位误差信号之间形成非线性。

公开(公告)号：US07102448B2

公开(公告)日：2006-09-05

申请号：US10812875

申请日：2004-03-31

申请人： Yu-Pin Chou ,  Yi-Shu Chang

发明人： Yu-Pin Chou ,  Yi-Shu Chang

IPC分类号： H03D13/00

CPC分类号： H03L7/089

摘要： A phase frequency detector used in a phase locked loop includes a phase error detecting unit for outputting phase error signals according to a phase error between a first input signal and a second input signal, and a reset unit coupled to the phase error detecting unit. The reset unit outputs reset signals according to the first and second input signals so as to reset the phase error detecting unit without delay time. Thus, it is possible to make the output timing of the phase error signal in a more precisely linear proportion to the phase error value and to enhance the sensitivity of the phase locked loop.

摘要翻译： 在锁相环中使用的相位频率检测器包括相位误差检测单元，用于根据第一输入信号和第二输入信号之间的相位误差输出相位误差信号，以及耦合到相位误差检测单元的复位单元。 复位单元根据第一和第二输入信号输出复位信号，以便无延迟时间复位相位误差检测单元。 因此，可以使相位误差信号的输出定时与相位误差值更精确地成线性比例，并提高锁相环的灵敏度。

公开(公告)号：US07945706B2

公开(公告)日：2011-05-17

申请号：US12128634

申请日：2008-05-29

申请人： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

发明人： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： H04N5/4401 ,  H04N5/46 ,  H04N5/765 ,  H04N21/42615 ,  H04N21/4305 ,  H04N21/436 ,  H04N21/4363

摘要： The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

摘要翻译： 本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。 信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。 输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子 对应于具有该组共享输入端的第二传输规范。 接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。