公开(公告)号：US20100184281A1

公开(公告)日：2010-07-22

申请号：US12355401

申请日：2009-01-16

申请人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

发明人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/268 ,  H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/268 ,  H01L29/4908 ,  H01L29/517

摘要： A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.

摘要翻译： 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供半导体衬底; 在所述衬底上形成具有界面层，高k电介质层和栅极层的一个或多个栅极堆叠; 以及对所述界面层进行至少一种处理，其中所述处理包括微波辐射处理，紫外线辐射处理或其组合。

公开(公告)号：US07910467B2

公开(公告)日：2011-03-22

申请号：US12355401

申请日：2009-01-16

申请人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

发明人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Liang-Gi Yao

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/28176 ,  H01L21/268 ,  H01L29/4908 ,  H01L29/517

摘要： A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.

摘要翻译： 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供半导体衬底; 在所述衬底上形成具有界面层，高k电介质层和栅极层的一个或多个栅极堆叠; 以及对所述界面层进行至少一种处理，其中所述处理包括微波辐射处理，紫外线辐射处理或其组合。

公开(公告)号：US11038056B2

公开(公告)日：2021-06-15

申请号：US13371169

申请日：2012-02-10

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20

摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

公开(公告)号：US20120025313A1

公开(公告)日：2012-02-02

申请号：US13272994

申请日：2011-10-13

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L27/12 ,  H01L29/02

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US08048723B2

公开(公告)日：2011-11-01

申请号：US12329279

申请日：2008-12-05

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L21/332

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20110037129A1

公开(公告)日：2011-02-17

申请号：US12912522

申请日：2010-10-26

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

摘要翻译： 提供具有多个翅片高度的半导体器件。 通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。 在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。 随后的蚀刻步骤在下面的衬底中形成对应的沟槽。 在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。 可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

公开(公告)号：US20090253266A1

公开(公告)日：2009-10-08

申请号：US12484911

申请日：2009-06-15

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L21/302

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

摘要翻译： 提供具有多个翅片高度的半导体器件。 通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。 在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。 随后的蚀刻步骤在下面的衬底中形成对应的沟槽。 在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。 可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

公开(公告)号：US20090250769A1

公开(公告)日：2009-10-08

申请号：US12484900

申请日：2009-06-15

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/78 ,  H01L27/088

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.

公开(公告)号：US20080230852A1

公开(公告)日：2008-09-25

申请号：US11714644

申请日：2007-03-06

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fun ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fun ,  Yu-Rung Hsu

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

摘要翻译： 半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。 第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。 第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。 第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同 厚度

公开(公告)号：US20110147810A1

公开(公告)日：2011-06-23

申请号：US12645834

申请日：2009-12-23

申请人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen

发明人： Yu-Rung Hsu ,  Chen-Hua Yu ,  Chao-Cheng Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.

摘要翻译： 本公开提供了一种半导体器件，其包括半导体衬底，设置在衬底的一部分上的栅极结构以及设置在衬底的该部分的任一侧的应变结构，并且由与半导体衬底不同的半导体材料形成。 衬底的部分是具有水平区域的垂直区域和从远离衬底表面的方向从水平区域延伸的垂直区域。