公开(公告)号：US08507979B1

公开(公告)日：2013-08-13

申请号：US13563470

申请日：2012-07-31

Applicant: Yuan-Sheng Huang ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Yuan-Sheng Huang ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括提供半导体衬底并在其中形成栅极沟槽。 该方法还包括用工作功能（WF）金属堆叠部分地填充栅极沟槽，并且在WF金属堆叠上用虚拟填充材料（DFM）填充剩余的栅极沟槽。 通过蚀刻在栅极沟槽中的WF金属堆叠形成子栅极沟槽，并且填充有绝缘体帽以在栅极沟槽中形成隔离区域。 DFM从栅极沟槽中的MG-中心沟槽（MGCT）被完全去除，其填充有填充金属。

公开(公告)号：US20130187235A1

公开(公告)日：2013-07-25

申请号：US13353975

申请日：2012-01-19

Applicant: Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

Inventor： Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.

Abstract translation: 本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。 栅介质层最少部分地缠绕在翅片结构的一段上。 栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。 本公开提供了制造FinFET的方法。 该方法包括提供包含半导体材料的翅片结构。 该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。 该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。 该方法包括在多晶硅层上形成伪栅极层。

公开(公告)号：US09287179B2

公开(公告)日：2016-03-15

申请号：US13353975

申请日：2012-01-19

Applicant: Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

Inventor： Yuan-Sheng Huang ,  Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Chao-Cheng Chen ,  Chia-Jen Chen

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.

Abstract translation: 本公开涉及FinFET。 FinFET包括在衬底上形成的翅片结构。 栅介质层最少部分地缠绕在翅片结构的一段上。 栅介质层包含高k栅介质材料。 FinFET包括在栅介质层上共形形成的多晶硅层。 FinFET包括在多晶硅层上形成的金属栅极电极层。 本公开提供了制造FinFET的方法。 该方法包括提供包含半导体材料的翅片结构。 该方法包括在鳍结构上方形成栅极电介质层，栅介质层至少部分地围绕翅片结构缠绕。 该方法包括在栅介质层上形成多晶硅层，其中多晶硅层以保形方式形成。 该方法包括在多晶硅层上形成伪栅极层。

公开(公告)号：US20130309834A1

公开(公告)日：2013-11-21

申请号：US13471649

申请日：2012-05-15

Applicant: Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

Inventor： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

IPC: H01L21/283 ,  H01L21/02

CPC classification number: H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括接收半导体器件，图案化第一硬掩模以在高电阻（Hi-R）堆叠中形成第一凹槽，去除第一硬掩模，在Hi-R堆叠中形成第二凹槽，形成第二 硬掩模在Hi-R堆叠的第二个凹槽中。 然后可以通过第二硬掩模和栅沟​​槽蚀刻在半导体衬底中形成HR。

公开(公告)号：US08691655B2

公开(公告)日：2014-04-08

申请号：US13471649

申请日：2012-05-15

Applicant: Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

Inventor： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

IPC: H01L21/02

CPC classification number: H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括接收半导体器件，图案化第一硬掩模以在高电阻（Hi-R）堆叠中形成第一凹槽，去除第一硬掩模，在Hi-R堆叠中形成第二凹槽，形成第二 硬掩模在Hi-R堆叠的第二个凹槽中。 然后可以通过第二硬掩模和栅沟​​槽蚀刻在半导体衬底中形成HR。

公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

Applicant: Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

Inventor： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC: H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US20130320410A1

公开(公告)日：2013-12-05

申请号：US13484047

申请日：2012-05-30

Applicant: Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L29/78 ,  H01L21/283 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

Abstract translation: 本发明涉及集成电路制造，更具体地涉及金属栅电极。 半导体器件的示例性结构包括：包括主表面的衬底; 主表面上的第一矩形栅电极，包括第一层多层材料; 与第一矩形栅电极的一侧相邻的第一电介质材料; 以及与所述第一矩形栅电极的其他3侧相邻的第二电介质材料，其中所述第一电介质材料和所述第二电介质材料共同围绕所述第一矩形栅电极。

公开(公告)号：US09991375B2

公开(公告)日：2018-06-05

申请号：US13484047

申请日：2012-05-30

Applicant: Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L21/283 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/283 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first rectangular gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first rectangular gate electrode; and a second dielectric material adjacent to the other 3 sides of the first rectangular gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first rectangular gate electrode.

公开(公告)号：US20120108046A1

公开(公告)日：2012-05-03

申请号：US13281862

申请日：2011-10-26

Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L21/308

CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。

公开(公告)号：US08273632B2

公开(公告)日：2012-09-25

申请号：US13281862

申请日：2011-10-26

Applicant: Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Ming-Ching Chang ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L21/32139 ,  H01L21/0276 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/823437 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成可图案化层。 该方法包括在可图案层上形成第一层。 该方法包括在第一层上形成第二层。 第二层比第一层薄得多。 该方法包括通过第一蚀刻工艺用光致抗蚀剂材料图案化第二层以形成图案化的第二层。 该方法包括通过第二蚀刻工艺将具有图案化的第二层的第一层图案化以形成图案化的第一层。 第一和第二层在第二蚀刻工艺期间具有显着不同的蚀刻速率。 该方法包括通过第三蚀刻工艺对具有图案化的第一层的图案化层进行图案化。