公开(公告)号：US08574928B2

公开(公告)日：2013-11-05

申请号：US13443818

申请日：2012-04-10

申请人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

发明人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC分类号： H01L21/00

CPC分类号： H01L27/222 ,  H01L43/12

摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

摘要翻译： 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US20130148417A1

公开(公告)日：2013-06-13

申请号：US13314470

申请日：2011-12-08

申请人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

发明人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/165

摘要： A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

摘要翻译： 描述了一种测试方法，其将具有不同强度的序列外部磁场施加到芯片或晶片中的MRAM单元（例如具有MTJ存储元件的那些），以选择性地筛选具有低或高热稳定性因子的单元。 矫顽力（Hc）用作热稳定因子（delta）的代表。 在各种实施例中，外部磁场的顺序，方向和强度用于确定不被正常场切换的高矫顽力单元以及通过选定的低场切换的低矫顽力单元。 在一些实施例中，MRAM的标准内部电流可用于切换电池。 可以使用标准的基于电路的电阻读取操作来确定每个单元对这些磁场的响应并识别异常的高和低矫顽力单元。

公开(公告)号：US20130267042A1

公开(公告)日：2013-10-10

申请号：US13443818

申请日：2012-04-10

申请人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

发明人： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC分类号： H01L21/02

CPC分类号： H01L27/222 ,  H01L43/12

摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

摘要翻译： 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US08553452B2

公开(公告)日：2013-10-08

申请号：US13314470

申请日：2011-12-08

申请人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

发明人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/165

摘要： A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

摘要翻译： 描述了一种测试方法，其将具有不同强度的序列外部磁场施加到芯片或晶片中的MRAM单元（例如具有MTJ存储元件的那些），以选择性地筛选具有低或高热稳定性因子的单元。 矫顽力（Hc）用作热稳定因子（delta）的代表。 在各种实施例中，外部磁场的顺序，方向和强度用于确定不被正常场切换的高矫顽力单元以及通过选定的低场切换的低矫顽力单元。 在一些实施例中，MRAM的标准内部电流可用于切换电池。 可以使用标准的基于电路的电阻读取操作来确定每个单元对这些磁场的响应并识别异常的高和低矫顽力单元。

公开(公告)号：US08796795B2

公开(公告)日：2014-08-05

申请号：US13136454

申请日：2011-08-01

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L45/00

CPC分类号： H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

摘要翻译： 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

公开(公告)号：US20130032907A1

公开(公告)日：2013-02-07

申请号：US13136454

申请日：2011-08-01

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

公开(公告)号：US08883520B2

公开(公告)日：2014-11-11

申请号：US13530381

申请日：2012-06-22

申请人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L21/00

CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L43/12

摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

摘要翻译： 描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。 一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。 另一个实施例分别对MTJ和底部电极进行图案化。 底部电极掩模然后覆盖底部电极下面的金属。 另一实施例将柱蚀刻工艺分为两个阶段。 第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。 蚀刻的第二阶段然后对剩余的层进行图案化。 另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

公开(公告)号：US20130341801A1

公开(公告)日：2013-12-26

申请号：US13530381

申请日：2012-06-22

申请人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L43/12

摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

公开(公告)号：US20130032775A1

公开(公告)日：2013-02-07

申请号：US13317564

申请日：2011-10-20

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

IPC分类号： H01L45/00

CPC分类号： H01L23/5226 ,  H01L27/222 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

摘要翻译： 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

公开(公告)号：US09520174B2

公开(公告)日：2016-12-13

申请号：US14754635

申请日：2015-06-29

申请人： Ebrahim Abedifard ,  Petro Estakhri

发明人： Ebrahim Abedifard ,  Petro Estakhri

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/56

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/5607

摘要： A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ.