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    Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line
    1.
    发明申请
    Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line 失效
    八个晶体管SRAM单元，只需要一个字线即可提高稳定性

    公开(公告)号：US20090034345A1

    公开(公告)日：2009-02-05

    申请号：US11832190

    申请日：2007-08-01

    申请人： Yuen H. Chan ,  William V. Huott ,  Donald W. Plass

    发明人： Yuen H. Chan ,  William V. Huott ,  Donald W. Plass

    IPC分类号： G11C7/00

    CPC分类号： G11C11/412 ,  G11C8/14

    摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

    摘要翻译： 由单个字线访问的SRAM单元和用于读取和写入操作的单独的存取晶体管。 一对写位线传输器件分别提供用于写操作的交叉耦合上拉，下拉晶体管对的右侧和左侧的访问以及与字线晶体管串联的单个读取位线晶体管，当 选中，读取单元格的内容。

    Eight transistor SRAM cell with improved stability requiring only one word line
    2.
    发明授权
    Eight transistor SRAM cell with improved stability requiring only one word line 失效
    八个晶体管SRAM单元具有改进的稳定性，只需要一个字线

    公开(公告)号：US07606060B2

    公开(公告)日：2009-10-20

    申请号：US11832190

    申请日：2007-08-01

    申请人： Yuen H. Chan ,  William V. Huott ,  Donald W. Plass

    发明人： Yuen H. Chan ,  William V. Huott ,  Donald W. Plass

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C8/14

    摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

    摘要翻译： 由单个字线访问的SRAM单元和用于读取和写入操作的单独的存取晶体管。 一对写位线传输器件分别提供用于写操作的交叉耦合上拉，下拉晶体管对的右侧和左侧的访问以及与字线晶体管串联的单个读取位线晶体管，当 选中，读取单元格的内容。

    Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy
    6.
    发明授权
    Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy 失效
    提供灵活的模块化冗余分配方法和设备，用于内置SRAM冗余自检的存储器

    公开(公告)号：US07219275B2

    公开(公告)日：2007-05-15

    申请号：US11053631

    申请日：2005-02-08

    申请人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

    发明人： Tom Y. Chang ,  William V. Huott ,  Thomas J. Knips ,  Donald W. Plass

    IPC分类号： G11C29/00 ,  G01R31/28

    CPC分类号： G11C29/802 ,  G11C11/41 ,  G11C29/44

    摘要： A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.

    摘要翻译： 一种为具有冗余的随机存取存储器的自检中构建的存储器提供灵活的模块冗余分配的方法和装置。 该装置包括第一冗余支持寄存器，其包括用于接收被测存储器中的位置的地址的输入，以及必须修复修复元件的数据。 该地址包括位置的行和列向量。 第一冗余支持寄存器还包括用于发送地址和数据的输出。 该装置还包括第二冗余支持寄存器，其包括用于从第一冗余支持寄存器的输出接收地址和数据的输入。 第二冗余支持寄存器的每个输入与第一冗余支持寄存器的每个输出共享一一对应关系。 该装置还包括用于提供第一冗余支持寄存器和第二冗余支持寄存器的模块化实现的分配逻辑。

    Integrated circuit chip with improved array stability
    8.
    发明授权
    Integrated circuit chip with improved array stability 有权
    集成电路芯片具有改进的阵列稳定性

    公开(公告)号：US07403412B2

    公开(公告)日：2008-07-22

    申请号：US11782282

    申请日：2007-07-24

    申请人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

    发明人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

    摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

    摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

    Integrated circuit chip with improved array stability
    9.
    发明授权
    Integrated circuit chip with improved array stability 有权
    集成电路芯片具有改进的阵列稳定性

    公开(公告)号：US07787284B2

    公开(公告)日：2010-08-31

    申请号：US12133450

    申请日：2008-06-05

    申请人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

    发明人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

    摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

    摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

    Integrated circuit chip with improved array stability
    10.
    发明授权
    Integrated circuit chip with improved array stability 失效
    集成电路芯片具有改进的阵列稳定性

    公开(公告)号：US07295457B2

    公开(公告)日：2007-11-13

    申请号：US10950940

    申请日：2004-09-27

    申请人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

    发明人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

    摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

    摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。