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公开(公告)号：US07437626B2
公开(公告)日：2008-10-14
申请号：US11056726
申请日：2005-02-11
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。
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2.发明申请Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy 失效高效的内存产品用于冗余的SRAM的测试和软修复公开(公告)号：US20080263417A1
公开(公告)日：2008-10-23
申请号：US12164869
申请日：2008-06-30
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。
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3.发明授权Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy 失效提供灵活的模块化冗余分配方法和设备，用于内置SRAM冗余自检的存储器公开(公告)号：US07219275B2
公开(公告)日：2007-05-15
申请号：US11053631
申请日：2005-02-08
CPC分类号： G11C29/802 , G11C11/41 , G11C29/44
摘要： A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.
摘要翻译： 一种为具有冗余的随机存取存储器的自检中构建的存储器提供灵活的模块冗余分配的方法和装置。 该装置包括第一冗余支持寄存器，其包括用于接收被测存储器中的位置的地址的输入，以及必须修复修复元件的数据。 该地址包括位置的行和列向量。 第一冗余支持寄存器还包括用于发送地址和数据的输出。 该装置还包括第二冗余支持寄存器，其包括用于从第一冗余支持寄存器的输出接收地址和数据的输入。 第二冗余支持寄存器的每个输入与第一冗余支持寄存器的每个输出共享一一对应关系。 该装置还包括用于提供第一冗余支持寄存器和第二冗余支持寄存器的模块化实现的分配逻辑。
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4.发明授权公开(公告)号：US07793173B2
公开(公告)日：2010-09-07
申请号：US12164869
申请日：2008-06-30
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。
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5.发明授权Method for self-correcting cache using line delete, data logging, and fuse repair correction 有权使用行删除，数据记录和保险丝修复校正自校正缓存的方法公开(公告)号：US07529997B2
公开(公告)日：2009-05-05
申请号：US11079816
申请日：2005-03-14
申请人： Patrick J. Meaney , William V. Huott , Thomas J. Knips , David J. Lund , Bryan L. Mechtly , Pradip Patel
发明人： Patrick J. Meaney , William V. Huott , Thomas J. Knips , David J. Lund , Bryan L. Mechtly , Pradip Patel
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C11/41 , G11C15/00 , G11C29/4401 , G11C29/789 , G11C2029/0407 , G11C2029/1208
摘要： An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.
摘要翻译： 一种用于保护计算机系统免受阵列可靠性故障的装置和方法使用阵列内置自检逻辑以及代码和硬件来删除有缺陷的高速缓存行或集合，识别相应的保险丝修复值，如果备用保险丝为主动式，则主动呼叫家庭 不可用，为下一次重新启动计划软保险丝修复，下次重新启动时计划行删除，在表中存储删除和保险丝修复（标记为电子序列号，删除时间戳或ABIST失败事件，地址和故障类型 ），并且如果有任何未被记录的遗漏的删除事件，则主动呼叫回家。 保险丝信息也可以更加永久地存储在硬件电子保险丝和/或EPROM中。 在重新启动期间，以前的修复可以应用于机器，以便ABIST将成功运行，以前的删除将通过检查进行维护，以允许由删除行保护的一些ABIST故障通过。
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6.发明授权公开(公告)号：US07064990B1
公开(公告)日：2006-06-20
申请号：US11053812
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C29/848
摘要： An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements. At least one spare memory element is configured at a size corresponding to one of the subcolumn elements. An input redundancy multiplexing stage and an output redundancy multiplexing stage are configured for steering around one or more defective memory array elements, and an input bit decoding stage and an output bit decoding stage are configured for implementing an additional, external multiplexing stage with respect to the input redundancy multiplexing stage and the output redundancy multiplexing stage.
摘要翻译： 用于在单个存储器阵列内实现多个存储器列冗余的装置包括内部划分为至少一对子列元素的多个存储器阵列元件。 至少一个备用存储器元件被配置为与子列元素之一对应的大小。 配置输入冗余多路复用级和输出冗余多路复用级用于围绕一个或多个有缺陷的存储器阵列元件转向，并且输入位解码级和输出位解码级用于实现相对于 输入冗余复用级和输出冗余复用级。
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7.发明授权Apparatus and method for implementing multiple memory redundancy with delay tracking clock 失效用延迟跟踪时钟实现多重存储冗余的装置和方法公开(公告)号：US07068554B1
公开(公告)日：2006-06-27
申请号：US11054272
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C29/842
摘要： A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.
摘要翻译： 存储器冗余控制装置包括静态比较级，其被配置为将请求的存储器地址的比特与表示缺陷存储器地址的相应的熔丝信息比特进行比较。 动态级被配置为接收静态比较级的输出，动态级的输出被预充电，以便最初去激活主子阵列解码电路。 动态级由其时钟信号进一步触发。 在激活时钟信号时，只要在请求的存储器地址和有缺陷的存储器地址之间存在匹配时，动态级的输出保持预充电，并且只要所请求的存储器地址和存储器地址之间存在不匹配，则动态级的输出被放电 有缺陷的内存地址。 延迟跟踪时钟发生器被配置为相对于动态级产生延迟跟踪时钟信号，以将动态级的输出门控到备用子阵列解码电路，其中每当动态级的输出被激活时，备用子阵列解码电路被激活 在激活时钟信号后仍保持预充电。
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8.发明授权ABIST data compression and serialization for memory built-in self test of SRAM with redundancy 失效ABIST数据压缩和串行化用于内存具有冗余的SRAM自检公开(公告)号：US07380191B2
公开(公告)日：2008-05-27
申请号：US11054566
申请日：2005-02-09
CPC分类号： G11C29/1201 , G11C11/41 , G11C29/40 , G11C29/48 , G11C29/802 , G11C2029/3602
摘要： A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.
摘要翻译： 一种实现ABIST数据压缩和串行化的方法和装置，用于具有冗余的SRAM的内存自检。 该方法包括提供为一个故障数据输出断言的检测信号，两个故障数据输出和大于两个故障数据输出。 该方法还包括用对应的二进制表示值来单独编码每个相应的故障数据输出的故障位位置。 该方法还包括串行化提供检测信号和单独编码的结果，并将序列化的结果发送到单个故障总线上的冗余支持寄存器功能。
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9.发明授权Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering 失效具有脉冲拉伸和冗余转向功能的快速脉冲供电NOR解码装置公开(公告)号：US07170320B2
公开(公告)日：2007-01-30
申请号：US11050933
申请日：2005-02-04
IPC分类号： H03K19/094 , H03K19/096
CPC分类号： H03K19/20
摘要： A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage. A pull up device restores the dynamic stage to a precharged condition, the pull up device controlled by a second clock signal independent of the first clock signal.
摘要翻译： 解码器电路包括具有多个扇入输入的脉冲供电级，由脉冲供电级馈送的动态级，以及通过传递器件选择性地耦合到脉冲供电级的输出节点的复制节点。 通过装置和动态级由时钟信号控制，以便能够利用动态级的时钟启用来对脉冲级的自定时评估。 上拉装置将动态级恢复到预充电状态，上拉装置由与第一时钟信号无关的第二时钟信号控制。
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公开(公告)号：US07009895B2
公开(公告)日：2006-03-07
申请号：US10814719
申请日：2004-03-31
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
CPC分类号： G11C29/806 , G11C29/848
摘要： The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track. This reduces the number of wire tracks from 1 track per I/O to 1 track per 2 I/Os.
摘要翻译： 所描述的方法使用跳过技术，其需要在待修复的块的输入和输出处的一组复用器。 实现I / O冗余控制逻辑的改进方法对芯片面积和芯片线轨都具有最小的影响。 为了克服在不期望的芯片上所需的房地产使用的问题，可以使用可以共享单个线路的奇数和偶数解码器输出，同样的线可用于奇数和偶数解码器输出。 为了实现作为集中功能的解码和携带功能，出现了逻辑上相邻的解码电路（通过进位信号连接的解码器）应物理上靠近在一起以最小化进位线路开销的要求。 如果解码结构和多路复用结构彼此正交配置，则每个解码器输出将需要线轨。 然而，所描述的方法允许奇数和偶数解码器输出共享相同的线轨道。 这减少了每个I / O从1个磁道到每2个I / O到1个磁道的电线轨迹数量。
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