公开(公告)号：US20120258575A1

公开(公告)日：2012-10-11

申请号：US13437271

申请日：2012-04-02

申请人： Yuhei SATO ,  Keiji SATO ,  Toshinari SASAKI ,  Tetsunori MARUYAMA ,  Atsuo ISOBE ,  Tsutomu MURAKAWA ,  Sachiaki TEZUKA

发明人： Yuhei SATO ,  Keiji SATO ,  Toshinari SASAKI ,  Tetsunori MARUYAMA ,  Atsuo ISOBE ,  Tsutomu MURAKAWA ,  Sachiaki TEZUKA

IPC分类号： H01L21/336

CPC分类号： H01L29/7869 ,  H01L21/477

摘要： To provide a highly reliable semiconductor device manufactured by giving stable electric characteristics to a semiconductor device including an oxide semiconductor. In a manufacturing process of a transistor, an oxide semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, a gate electrode layer, and an aluminum oxide film are formed in this order, and then heat treatment is performed on the oxide semiconductor layer and the aluminum oxide film, whereby an oxide semiconductor layer from which an impurity containing a hydrogen atom is removed and which includes a region containing oxygen more than the stoichiometric proportion is formed. In addition, when the aluminum oxide film is formed, entry and diffusion of water or hydrogen into the oxide semiconductor layer from the air due to heat treatment in a manufacturing process of a semiconductor device or an electronic appliance including the transistor can be prevented.

摘要翻译： 提供通过给包括氧化物半导体的半导体器件赋予稳定的电特性而制造的高可靠性的半导体器件。 在晶体管的制造工序中，依次形成氧化物半导体层，源极电极层，漏极电极层，栅极绝缘膜，栅电极层和氧化铝膜，然后进行热处理 在氧化物半导体层和氧化铝膜上形成除去含有氢原子的杂质的氧化物半导体层，其中含有超过化学计量比的氧的区域。 此外，当形成氧化铝膜时，可以防止在半导体器件或包括晶体管的电子设备的制造过程中由于热处理而从空气中进入和扩散水或氢进入氧化物半导体层。

公开(公告)号：US20130075722A1

公开(公告)日：2013-03-28

申请号：US13613192

申请日：2012-09-13

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

IPC分类号： H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/7869

摘要： A highly reliable structure for high-speed response and high-speed driving of a semiconductor device, in which on-state characteristics of a transistor are increased is provided. In the coplanar transistor, an oxide semiconductor layer, a source and drain electrode layers including a stack of a first conductive layer and a second conductive layer, a gate insulating layer, and a gate electrode layer are sequentially stacked in this order. The gate electrode layer is overlapped with the first conductive layer with the gate insulating layer provided therebetween, and is not overlapped with the second conductive layer with the gate insulating layer provided therebetween.

摘要翻译： 提供了一种用于高速响应和高速驱动半导体器件的高度可靠的结构，其中晶体管的导通状态特性增加。 在共面晶体管中，依次层叠氧化物半导体层，包括第一导电层和第二导电层的堆叠的源极和漏极电极层，栅极绝缘层和栅极电极层。 栅极电极层与第一导电层重叠，栅极绝缘层设置在它们之间，并且与其间设置有栅极绝缘层的第二导电层不重叠。

公开(公告)号：US20130069055A1

公开(公告)日：2013-03-21

申请号：US13608044

申请日：2012-09-10

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromachi GODO ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Naoto YAMADE ,  Junichi KOEZUKA

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Hiromachi GODO ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Naoto YAMADE ,  Junichi KOEZUKA

IPC分类号： H01L29/78

CPC分类号： H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693

摘要： Provided is a semiconductor device in which an oxide semiconductor layer is provided; a pair of wiring layers which are provided with the gate electrode layer interposed therebetween are electrically connected to the low-resistance regions; and electrode layers are provided to be in contact with the low-resistance regions, below regions where the wiring layers are formed.

摘要翻译： 提供一种半导体器件，其中提供氧化物半导体层; 设置有栅极电极层的一对布线层电连接到低电阻区域; 并且电极层设置成与低电阻区域接触，在形成布线层的区域之下。

公开(公告)号：US20130069053A1

公开(公告)日：2013-03-21

申请号：US13608039

申请日：2012-09-10

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshinari SASAKI

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshinari SASAKI

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L27/1218 ,  H01L27/1225

摘要： To provide a transistor which includes an oxide semiconductor and is capable of operating at high speed or a highly reliable semiconductor device including the transistor, a transistor in which an oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer, which is embedded in a base insulating layer and whose upper surface is at least partly exposed from the base insulating layer, and a wiring layer provided above the oxide semiconductor layer is electrically connected to the electrode layer or a part of a low-resistance region of the oxide semiconductor layer, which overlaps with the electrode layer.

公开(公告)号：US20120286270A1

公开(公告)日：2012-11-15

申请号：US13463092

申请日：2012-05-03

申请人： Atsuo ISOBE ,  Toshinari SASAKI ,  Junichi KOEZUKA ,  Shunpei YAMAZAKI

发明人： Atsuo ISOBE ,  Toshinari SASAKI ,  Junichi KOEZUKA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L21/02565 ,  H01L21/265 ,  H01L21/425 ,  H01L21/84 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78693

摘要： It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

摘要翻译： 本发明的目的是提供一种抑制短路效应并实现小型化的半导体器件及其制造方法。 在绝缘层中形成沟槽，并且将杂质添加到与沟槽的上端角部接触的氧化物半导体膜，由此形成源极区域和漏极区域。 利用上述结构，可以实现小型化。 此外，利用沟槽，即使当源电极层和漏电极层之间的距离缩短时，也可以适当地抑制沟槽的深度适当地设定短沟道效应。

公开(公告)号：US20130075721A1

公开(公告)日：2013-03-28

申请号：US13613178

申请日：2012-09-13

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshinari SASAKI

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshinari SASAKI

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/10 ,  H01L29/41733 ,  H01L29/41775

摘要： Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.

摘要翻译： 提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。 晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。 此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

公开(公告)号：US20130069054A1

公开(公告)日：2013-03-21

申请号：US13608042

申请日：2012-09-10

申请人： Atsuo ISOBE ,  Toshinari SASAKI

发明人： Atsuo ISOBE ,  Toshinari SASAKI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/1225 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/7869

摘要： In a semiconductor device including an oxide semiconductor layer, a conductive layer is formed in contact with a lower portion of the oxide semiconductor layer and treatment for adding an impurity is performed, so that a channel formation region and a pair of low-resistance regions between which the channel formation region is sandwiched are formed in the oxide semiconductor layer in a self-aligned manner. Wiring layers electrically connected to the conductive layer and the low-resistance regions are provided in openings of an insulating layer.

摘要翻译： 在包括氧化物半导体层的半导体器件中，形成与氧化物半导体层的下部接触的导电层，并且进行用于添加杂质的处理，使得沟道形成区域和一对低电阻区域在 在自对准的方式在氧化物半导体层中形成夹着沟道形成区域的区域。 电连接到导电层和低电阻区域的接线层设置在绝缘层的开口中。

公开(公告)号：US20120267709A1

公开(公告)日：2012-10-25

申请号：US13446026

申请日：2012-04-13

申请人： Atsuo ISOBE ,  Toshinari SASAKI

发明人： Atsuo ISOBE ,  Toshinari SASAKI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78603 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/7869 ,  H01L29/78696

摘要： To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.

摘要翻译： 提供高度可靠的半导体器件。 提供一种防止缺陷并实现小型化的半导体器件。 形成与包括沟槽的绝缘层接触的用作源区或漏区的区域的厚度大于用作沟道形成区的区的厚度的氧化物半导体层。 在包括氧化物半导体层的晶体管中，可以抑制阈值电压的变化，电特性的劣化和正常的导通，可以降低源电阻或漏极电阻，从而晶体管可以具有高的可靠性。

公开(公告)号：US20120267624A1

公开(公告)日：2012-10-25

申请号：US13446028

申请日：2012-04-13

申请人： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

发明人： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/24 ,  H01L21/34

CPC分类号： H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02667 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

摘要： An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

摘要翻译： 绝缘层设置有突出的结构体，并且设置与突出结构体接触的氧化物半导体层的沟道形成区域，由此沟道形成区域沿三维方向（垂直于衬底的方向）延伸 ）。 因此，可以使晶体管小型化并且延长晶体管的有效沟道长度。 此外，突出结构体的顶表面和侧表面彼此相交的突出结构体的上端角部弯曲，并且氧化物半导体层形成为包括具有c轴的晶体 垂直于曲面。

公开(公告)号：US20120267696A1

公开(公告)日：2012-10-25

申请号：US13446020

申请日：2012-04-13

申请人： Atsuo ISOBE ,  Toshinari SASAKI

发明人： Atsuo ISOBE ,  Toshinari SASAKI

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L29/78696 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02667 ,  H01L23/564 ,  H01L27/1052 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.

摘要翻译： 将稳定的电特性和高可靠性提供给包括氧化物半导体的小型化和集成的半导体器件。 在包括氧化物半导体膜的晶体管（半导体器件）中，氧化物半导体膜沿着形成在绝缘层中的沟槽（沟槽）设置。 沟槽包括具有曲率半径大于或等于20nm且小于或等于60nm的弯曲形状的下端拐角部分，并且氧化物半导体膜设置成与底表面接触，下端 拐角部分和沟槽的内壁表面。 氧化物半导体膜包括具有基本上垂直于至少在下端拐角部分的表面的c轴的晶体。