公开(公告)号：US20130075722A1

公开(公告)日：2013-03-28

申请号：US13613192

申请日：2012-09-13

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yutaka OKAZAKI ,  Takehisa HATANO ,  Sachiaki TEZUKA ,  Suguru HONDO ,  Toshihiko SAITO

IPC分类号： H01L29/786

CPC分类号： H01L29/41733 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/7869

摘要： A highly reliable structure for high-speed response and high-speed driving of a semiconductor device, in which on-state characteristics of a transistor are increased is provided. In the coplanar transistor, an oxide semiconductor layer, a source and drain electrode layers including a stack of a first conductive layer and a second conductive layer, a gate insulating layer, and a gate electrode layer are sequentially stacked in this order. The gate electrode layer is overlapped with the first conductive layer with the gate insulating layer provided therebetween, and is not overlapped with the second conductive layer with the gate insulating layer provided therebetween.

摘要翻译： 提供了一种用于高速响应和高速驱动半导体器件的高度可靠的结构，其中晶体管的导通状态特性增加。 在共面晶体管中，依次层叠氧化物半导体层，包括第一导电层和第二导电层的堆叠的源极和漏极电极层，栅极绝缘层和栅极电极层。 栅极电极层与第一导电层重叠，栅极绝缘层设置在它们之间，并且与其间设置有栅极绝缘层的第二导电层不重叠。

公开(公告)号：US20120187397A1

公开(公告)日：2012-07-26

申请号：US13356012

申请日：2012-01-23

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC分类号： H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

摘要翻译： 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

公开(公告)号：US20130075733A1

公开(公告)日：2013-03-28

申请号：US13609931

申请日：2012-09-11

申请人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Sho NAGAMATSU

发明人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Sho NAGAMATSU

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/463 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/04 ,  H01L29/78 ,  H01L29/7869

摘要： A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

摘要翻译： 一分钟晶体管和微晶体管的制造方法。 源极电极层和漏极电极层各自形成在形成在覆盖半导体层的绝缘层中的对应的开口中。 源电极层的开口和漏电极层的开口分开形成两个不同的步骤。 源极电极层和漏电极层通过在绝缘层上和开口中沉积导电层而形成，然后通过抛光去除绝缘层上方的部分。 该制造方法允许稍后的源极电极和漏极电极层彼此靠近并且靠近半导体层的沟道形成区域。 这种结构导致即使在微小结构的情况下也具有高电特性和高制造成品率的晶体管。

公开(公告)号：US20130075732A1

公开(公告)日：2013-03-28

申请号：US13604962

申请日：2012-09-06

申请人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

发明人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.

摘要翻译： 提供具有高电特性的小型化晶体管，其产率高。 在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。 在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与 氧化物半导体膜和侧壁绝缘层。 在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜 通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

公开(公告)号：US20120223306A1

公开(公告)日：2012-09-06

申请号：US13409316

申请日：2012-03-01

申请人： Toshihiko SAITO ,  Kiyoshi KATO ,  Atsuo ISOBE

发明人： Toshihiko SAITO ,  Kiyoshi KATO ,  Atsuo ISOBE

IPC分类号： H01L29/78

CPC分类号： H01L27/0688 ,  G11C16/0433 ,  H01L21/02565 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

摘要： With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

摘要翻译： 通过包括氧化物半导体材料的晶体管和包括除了氧化物半导体之外的半导体材料的晶体管的组合，具有可以长时间保持数据并且对数字没有限制的新颖结构的半导体器件 的写作可以获得。 当用于将包括氧化物半导体的半导体材料的晶体管连接到包括氧化物半导体材料的晶体管的连接电极小于包含与连接电极连接的氧化物半导体以外的半导体材料的晶体管的电极时， 具有新颖结构的半导体器件可以高度集成，并且可以增加每单位面积的存储容量。

公开(公告)号：US20120139872A1

公开(公告)日：2012-06-07

申请号：US13367634

申请日：2012-02-07

申请人： Kiyoshi KATO ,  Toshihiko SAITO

发明人： Kiyoshi KATO ,  Toshihiko SAITO

IPC分类号： G09G3/36 ,  G06F3/045

CPC分类号： G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

摘要： A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

摘要翻译： 可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。 具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。

公开(公告)号：US20110204365A1

公开(公告)日：2011-08-25

申请号：US13026525

申请日：2011-02-14

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： H01L29/786

CPC分类号： H01L27/1052 ,  H01L27/088 ,  H01L27/11524 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/0649 ,  H01L29/247 ,  H01L29/42328 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/788

摘要： At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

摘要翻译： 高度集成在元件中的多个晶体管中的至少一个设置有后栅，而不增加制造步骤的数量。 在包括纵向层叠的多个晶体管的元件中，上部的至少一个晶体管包括具有半导体特性的金属氧化物，与下部晶体管的栅电极相同的层被设置为与沟道重叠 上部的晶体管的形成区域和与栅极电极相同的层的一部分用作上部晶体管的背栅极。 被覆盖有绝缘层的下部的晶体管进行平坦化处理，从而使栅电极暴露并连接到作为上部晶体管的源电极和漏电极的层。

公开(公告)号：US20110097861A1

公开(公告)日：2011-04-28

申请号：US12984139

申请日：2011-01-04

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： H01L21/8242 ,  H01L21/02

CPC分类号： H01L27/28 ,  G11C5/025 ,  G11C8/08 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1255 ,  H01L28/40

摘要： An object of the invention is to reduce an area occupied by a capacitor in a circuit in a semiconductor device, and to downsize a semiconductor device on which the capacitor and an organic memory are mounted. The organic memory and the capacitor, included in a peripheral circuit, in which the same material as the layer containing the organic compound used for the organic memory is used as a dielectric, are used. The peripheral circuit here means a circuit having at least a capacitor such as a resonance circuit, a power supply circuit, a boosting circuit, a DA converter, or a protective circuit. Further, a capacitor in which a semiconductor is used as a dielectric may be provided over the same substrate as well as the capacitor in which the same material as the layer containing the organic compound is used as a dielectric. In this case, it is desirable that the capacitor in which the same material as the layer containing the organic compound is used as a dielectric and the capacitor in which the semiconductor is used as a dielectric are connected to each other in parallel.

摘要翻译： 本发明的一个目的是减少半导体器件的电路中的电容器所占的面积，并且减小其上安装有电容器和有机存储器的半导体器件。 使用包含在外围电路中的有机存储器和电容器，其中与用于有机存储器的有机化合物的层相同的材料用作电介质。 这里的外围电路是指至少具有诸如谐振电路，电源电路，升压电路，DA转换器或保护电路的电容器的电路。 此外，可以在与使用与含有有机化合物的层相同的材料作为电介质的电容器的同一基板上设置将半导体用作电介质的电容器。 在这种情况下，期望使用与含有有机化合物的层相同的材料作为电介质的电容器和将半导体用作电介质的电容器彼此并联连接。

公开(公告)号：US20110080774A1

公开(公告)日：2011-04-07

申请号：US12890856

申请日：2010-09-27

申请人： Toshihiko SAITO ,  Takanori MATSUZAKI

发明人： Toshihiko SAITO ,  Takanori MATSUZAKI

IPC分类号： G11C11/56 ,  H01L45/00

CPC分类号： G11C13/004 ,  G11C17/16 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/24

摘要： Objects of the present invention are to improve the manufacturing yield of semiconductor devices, reduce manufacturing cost of the semiconductor device, and reduce the circuit area of an integrated circuit included in the semiconductor device. A memory layer of a memory element and a resistive layer of a resistor included in the semiconductor device are formed of the same material. Therefore, the memory layer and the resistive layer are formed in the same step, whereby the number of manufacturing steps of the semiconductor device can be reduced. As a result, the manufacturing yield of the semiconductor devices can be improved and the manufacturing cost can be reduced. In addition, the semiconductor device includes a resistor having a resistive component which has high resistance value. Consequently, the area of the integrated circuit included in the semiconductor device can be reduced.

摘要翻译： 本发明的目的是提高半导体器件的制造成品率，降低半导体器件的制造成本，并且减小包括在半导体器件中的集成电路的电路面积。 存储元件的存储层和包含在半导体器件中的电阻器的电阻层由相同的材料形成。 因此，在相同的步骤中形成存储层和电阻层，从而可以减少半导体器件的制造步骤的数量。 结果，可以提高半导体器件的制造成品率，并且可以降低制造成本。 此外，半导体器件包括具有高电阻值的电阻元件的电阻器。 因此，可以减少包括在半导体器件中的集成电路的面积。

公开(公告)号：US20110284838A1

公开(公告)日：2011-11-24

申请号：US13107270

申请日：2011-05-13

申请人： Toshihiko SAITO

发明人： Toshihiko SAITO

IPC分类号： H01L29/04

CPC分类号： H01L27/1225 ,  G11C5/005 ,  G11C7/02 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/18 ,  G11C16/349 ,  H01L27/10873 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1255 ,  H01L28/60

摘要： One object is to propose a memory device in which a period in which data is held can be ensured and memory capacity per unit area can be increased. The memory device includes a memory element, a transistor including an oxide semiconductor in an active layer for control of accumulating, holding, and discharging charge in the memory element, and a capacitor connected to the memory element. At least one of a pair of electrodes of the capacitor has a light-blocking property. Further, the memory device includes a light-blocking conductive film or a light-blocking insulating film. The active layer is positioned between the electrode having a light-blocking property and the light-blocking conductive film or the light-blocking insulating film.

摘要翻译： 一个目的是提出一种存储装置，其中可以确保保持数据的周期，并且可以增加每单位面积的存储容量。 存储器件包括存储元件，包括用于控制存储元件中的电荷的累积，保持和放电的有源层中的氧化物半导体的晶体管以及连接到存储元件的电容器。 电容器的一对电极中的至少一个具有阻光性。 此外，存储器件包括遮光导电膜或遮光绝缘膜。 有源层位于具有阻光性的电极和遮光导电膜或遮光绝缘膜之间。