公开(公告)号：US08334959B2

公开(公告)日：2012-12-18

申请号：US11492014

申请日：2006-07-25

申请人： Yukiya Hirabayashi ,  Takashi Sato

发明人： Yukiya Hirabayashi ,  Takashi Sato

IPC分类号： G02F1/1345 ,  G02F1/1333 ,  G02F1/1339 ,  G09G3/36 ,  G09G5/00 ,  G06F3/038

CPC分类号： G02F1/136204 ,  G02F2202/103 ,  G02F2202/22 ,  G09G3/3648 ,  G09G2330/04 ,  H01L27/0251 ,  H01L27/12 ,  H01L27/124

摘要： An electro-optical device having a display region in which a plurality of pixels are arranged in a matrix includes: switching elements each corresponding to one the plurality of pixels; a first sealed wiring portion that is formed on an element substrate so as to surround at least three sides of the display region; and a second sealed wiring portion that surrounds the first sealed wiring portion.

摘要翻译： 具有其中多个像素排列成矩阵的显示区域的电光装置包括：各自对应于多个像素中的一个的开关元件; 第一密封布线部，其形成在元件基板上，以围绕所述显示区域的至少三个边; 以及包围第一密封布线部的第二密封布线部。

公开(公告)号：US20070030434A1

公开(公告)日：2007-02-08

申请号：US11492014

申请日：2006-07-25

申请人： Yukiya Hirabayashi ,  Takashi Sato

发明人： Yukiya Hirabayashi ,  Takashi Sato

IPC分类号： G02F1/1345

CPC分类号： G02F1/136204 ,  G02F2202/103 ,  G02F2202/22 ,  G09G3/3648 ,  G09G2330/04 ,  H01L27/0251 ,  H01L27/12 ,  H01L27/124

摘要： An electro-optical device having a display region in which a plurality of pixels are arranged in a matrix includes: switching elements each corresponding to one the plurality of pixels; a first sealed wiring portion that is formed on an element substrate so as to surround at least three sides of the display region; and a second sealed wiring portion that surrounds the first sealed wiring portion.

摘要翻译： 具有其中多个像素排列成矩阵的显示区域的电光装置包括：各自对应于多个像素中的一个的开关元件; 第一密封布线部，其形成在元件基板上，以围绕所述显示区域的至少三个边; 以及包围第一密封布线部的第二密封布线部。

公开(公告)号：US20070281430A1

公开(公告)日：2007-12-06

申请号：US11785219

申请日：2007-04-16

申请人： Yukiya Hirabayashi ,  Takashi Sato ,  Yutaka Sano

发明人： Yukiya Hirabayashi ,  Takashi Sato ,  Yutaka Sano

IPC分类号： H01L21/336

CPC分类号： H01L27/124 ,  H01L27/1255

摘要： An electro-optical device includes pixel regions arranged at intersections of a plurality of data lines and a plurality of scanning lines on an element substrate. A sensor element, a sensor signal line for outputting a signal from the sensor element, a common wiring line, and a capacitive-coupling-operation bidirectional diode element are disposed at an end of a region on the element substrate in which the pixel regions are arranged. The capacitive-coupling-operation bidirectional diode element includes two capacitive-coupling-operation diode elements each including a semiconductor element including a source electrode, a drain electrode, a semiconductor layer having a channel region, and a gate electrode facing the channel region with a gate insulating film disposed therebetween, and a capacitor element arranged between one of the source electrode and the drain electrode and the gate electrode, the two capacitive-coupling-operation diode elements being electrically connected in opposite directions to each other. The sensor signal line is electrically connected to the common wiring line via the capacitive-coupling-operation bidirectional diode element. A control wiring line for supplying a gate voltage setting the semiconductor elements of the capacitive-coupling-operation bidirectional diode element to be in a non-conducting state is disposed for the capacitive-coupling-operation bidirectional diode element.

摘要翻译： 电光装置包括配置在元件基板上的多条数据线和多条扫描线的交点处的像素区域。 传感器元件，用于输出来自传感器元件的信号的传感器信号线，公共布线和电容耦合操作双向二极管元件设置在元件基板上的像素区域为 安排。 电容耦合操作双向二极管元件包括两个电容耦合操作二极管元件，每个二极管元件包括半导体元件，该半导体元件包括源电极，漏电极，具有沟道区的半导体层，以及面向沟道区的栅电极， 设置在它们之间的栅极绝缘膜，以及布置在源极和漏极之间的一个电容器元件和栅电极，两个电容耦合操作二极管元件彼此相反地电连接。 传感器信号线通过电容耦合操作双向二极管元件电连接到公共布线。 为了将电容耦合操作双向二极管元件的半导体元件设定为非导通状态的栅极电压，设置用于电容耦合操作双向二极管元件的控制布线。

公开(公告)号：US20070262352A1

公开(公告)日：2007-11-15

申请号：US11730287

申请日：2007-03-30

申请人： Yukiya Hirabayashi ,  Takashi Sato

发明人： Yukiya Hirabayashi ,  Takashi Sato

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： G02F1/136213 ,  G02F2201/40 ,  G02F2202/103 ,  G02F2202/42 ,  H01L27/1255

摘要： An electro-optical device includes an element substrate having a plurality of pixel regions; thin-film transistors, arranged in the pixel regions, including gate electrodes, portions of a gate insulating layer, and semiconductor layers; pixel electrodes electrically connected to drain regions of the thin-film transistors; and storage capacitors including lower electrodes and upper electrodes that are opposed to the lower electrodes with insulating layers disposed therebetween, the insulating layers being made of the same material as that for forming the gate insulating layer. The upper electrodes overlap with some of end portions of the lower electrodes. The gate insulating layer has thin portions located in inner portions of regions overlapping with the lower and upper electrodes and thick portions which are located in regions overlapping with the upper electrodes and the end portions of the lower electrodes and which have a thickness greater than that of the thin portions.

摘要翻译： 电光装置包括具有多个像素区域的元件基板; 布置在像素区域中的薄膜晶体管，包括栅电极，栅极绝缘层的部分和半导体层; 电连接到薄膜晶体管的漏极区域的像素电极; 以及包括与设置在其间的绝缘层相对的下电极的下电极和上电极的存储电容器，所述绝缘层由与用于形成栅极绝缘层的材料相同的材料制成。 上电极与下电极的一些端部重叠。 栅绝缘层具有位于与下电极和上电极重叠的区域的内部的薄部分和位于与上电极和下电极的端部重叠的区域中的厚部分，其厚度大于 薄的部分。

公开(公告)号：US07619256B2

公开(公告)日：2009-11-17

申请号：US11730287

申请日：2007-03-30

申请人： Yukiya Hirabayashi ,  Takashi Sato

发明人： Yukiya Hirabayashi ,  Takashi Sato

IPC分类号： H01L27/14

CPC分类号： G02F1/136213 ,  G02F2201/40 ,  G02F2202/103 ,  G02F2202/42 ,  H01L27/1255

摘要： An electro-optical device includes an element substrate having a plurality of pixel regions; thin-film transistors, arranged in the pixel regions, including gate electrodes, portions of a gate insulating layer, and semiconductor layers; pixel electrodes electrically connected to drain regions of the thin-film transistors; and storage capacitors including lower electrodes and upper electrodes that are opposed to the lower electrodes with insulating layers disposed therebetween, the insulating layers being made of the same material as that for forming the gate insulating layer. The upper electrodes overlap with some of end portions of the lower electrodes. The gate insulating layer has thin portions located in inner portions of regions overlapping with the lower and upper electrodes and thick portions which are located in regions overlapping with the upper electrodes and the end portions of the lower electrodes and which have a thickness greater than that of the thin portions.

摘要翻译： 电光装置包括具有多个像素区域的元件基板; 布置在像素区域中的薄膜晶体管，包括栅电极，栅极绝缘层的部分和半导体层; 电连接到薄膜晶体管的漏极区域的像素电极; 以及包括与设置在其间的绝缘层相对的下电极的下电极和上电极的存储电容器，所述绝缘层由与用于形成栅极绝缘层的材料相同的材料制成。 上电极与下电极的一些端部重叠。 栅绝缘层具有位于与下电极和上电极重叠的区域的内部的薄部分和位于与上电极和下电极的端部重叠的区域中的厚部分，其厚度大于 薄的部分。

公开(公告)号：US07569885B2

公开(公告)日：2009-08-04

申请号：US11785219

申请日：2007-04-16

申请人： Yukiya Hirabayashi ,  Takashi Sato ,  Yutaka Sano

发明人： Yukiya Hirabayashi ,  Takashi Sato ,  Yutaka Sano

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/124 ,  H01L27/1255

摘要： An electro-optical device includes pixel regions arranged at intersections of a plurality of data lines and a plurality of scanning lines on an element substrate. A sensor element, a sensor signal line for outputting a signal from the sensor element, a common wiring line, and a capacitive-coupling-operation bidirectional diode element are disposed at an end of a region on the element substrate in which the pixel regions are arranged. The capacitive-coupling-operation bidirectional diode element includes two capacitive-coupling-operation diode elements each including a semiconductor element including a source electrode, a drain electrode, a semiconductor layer having a channel region, and a gate electrode facing the channel region with a gate insulating film disposed therebetween, and a capacitor element arranged between one of the source electrode and the drain electrode and the gate electrode.

摘要翻译： 电光装置包括配置在元件基板上的多条数据线和多条扫描线的交点处的像素区域。 传感器元件，用于输出来自传感器元件的信号的传感器信号线，公共布线和电容耦合操作双向二极管元件设置在元件基板上的像素区域为 安排。 电容耦合操作双向二极管元件包括两个电容耦合操作二极管元件，每个二极管元件包括半导体元件，该半导体元件包括源电极，漏电极，具有沟道区的半导体层，以及面向沟道区的栅电极， 设置在它们之间的栅极绝缘膜，以及布置在源极电极和漏极电极之间的电容器元件和栅电极。

公开(公告)号：US06852653B2

公开(公告)日：2005-02-08

申请号：US09970766

申请日：2001-10-05

申请人： Yasushi Yamazaki ,  Yukiya Hirabayashi

发明人： Yasushi Yamazaki ,  Yukiya Hirabayashi

IPC分类号： G02F1/1333 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09F9/30 ,  H01L21/02 ,  H01L21/336 ,  H01L21/762 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/30 ,  H01L21/46 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1203 ,  H01L27/1214 ,  Y10S438/977 ,  Y10S438/978

摘要： A method of manufacturing a semiconductor substrate (7) includes the processes of: forming an insulation film (2) on a surface of a semiconductor substrate main body (1); forming an ion shield member (3) having a predetermined shape on the insulation film; implanting an ion into the semiconductor substrate main body from a side on which the insulation film is formed, to thereby form an ion implantation layer (1a, 1b); removing the ion shield member; laminating the insulation film and a support substrate (5) onto each other; and separating the semiconductor substrate main body from the support substrate at a portion of the ion implantation layer.

摘要翻译： 一种制造半导体衬底（7）的方法包括以下工艺：在半导体衬底主体（1）的表面上形成绝缘膜（2）; 在所述绝缘膜上形成具有预定形状的离子屏蔽构件（3）; 从形成绝缘膜的一侧将离子注入到半导体衬底主体中，从而形成离子注入层（1a，1b）; 去除离子屏蔽构件; 将绝缘膜和支撑基板（5）彼此层叠; 并且在离子注入层的一部分处将半导体衬底主体与支撑衬底分离。

公开(公告)号：US06734940B2

公开(公告)日：2004-05-11

申请号：US09776678

申请日：2001-02-06

申请人： Yukiya Hirabayashi

发明人： Yukiya Hirabayashi

IPC分类号： G02F11333

CPC分类号： G02F1/136204

摘要： Methods and systems are provided for securely preventing cracking or peeling of an insulating film in the periphery of a cutting portion of cutting short-circuit wiring by etching in a substrate, such as a liquid crystal device substrate that includes short-circuit wiring for a measure against static electricity. In particular, in the liquid crystal device substrate, cutting holes are provided by etching in a first interlayer insulating film and a second interlayer insulating film, which cover short-circuit wiring provided as electrostatic measure wiring, for cutting the short-circuit wiring. An etching stop layer made of a single crystal silicon film having resistance to etching of the second interlayer insulating film is formed in a wider range than the cutting holes between the short-circuit wiring and the buried oxide film.

摘要翻译： 提供了一种方法和系统，用于通过在包括用于测量的短路布线的诸如液晶装置基板的基板中进行蚀刻来可靠地防止在切割短路布线的切割部分的周边中的绝缘膜的破裂或剥离 防静电。 特别地，在液晶装置基板中，通过蚀刻在第一层间绝缘膜和第二层间绝缘膜中设置切割孔，该第二层间绝缘膜覆盖设置为静电测量布线的短路布线，用于切断短路布线。 在具有耐蚀刻第二层间绝缘膜的单晶硅膜制成的蚀刻停止层形成在比短路布线和掩埋氧化膜之间的切割孔更宽的范围内。

公开(公告)号：US06594064B2

公开(公告)日：2003-07-15

申请号：US09832198

申请日：2001-04-11

申请人： Yukiya Hirabayashi

发明人： Yukiya Hirabayashi

IPC分类号： G02F107

CPC分类号： G02F1/136209 ,  G02F1/136213 ,  G02F2001/13613 ,  G02F2202/105

摘要： To prevent the substrate floating effect that is caused when a transistor channel region fabricated of a monocrystal silicon layer covered with an insulator is in a floating state, and to stabilize the electrical characteristics of the transistor. A channel region of a semiconductor layer includes an extension portion. The end of the extension portion is connected to a contact hole. The contact hole is in turn connected to an interconnect line. The interconnect line is configured with one end thereof connected to the contact hole and with the other end connected to a contact hole leading to a light-shielding layer.

摘要翻译： 为了防止在由绝缘体覆盖的单晶硅层制造的晶体管沟道区域处于浮置状态时产生的衬底浮置效应，并且稳定晶体管的电特性。 半导体层的沟道区域包括延伸部分。 延伸部分的端部连接到接触孔。 接触孔又连接到互连线。 互连线被构造成其一端连接到接触孔，另一端连接到通向遮光层的接触孔。

公开(公告)号：US20120044132A1

公开(公告)日：2012-02-23

申请号：US13030409

申请日：2011-02-18

申请人： Masayuki Koga ,  Yukiya Hirabayashi

发明人： Masayuki Koga ,  Yukiya Hirabayashi

IPC分类号： G09G3/36 ,  G09G5/00 ,  G11C19/00

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2300/0413 ,  G11C19/28

摘要： Disclosed herein is a shift register including shift register unit circuits of a plurality of stages. Each of the shift register unit circuits of the plurality of stages includes a first transistor having a source and a drain to one of which a first clock signal is input and a gate to which a second clock signal obtained by substantially inverting the first clock signal is input. When the second clock signal at one of an H level and an L level is input to the gate of the first transistor, the first clock signal at the other of the H level and the L level is input to one of the source and the drain of the first transistor.

摘要翻译： 这里公开了包括多级的移位寄存器单元电路的移位寄存器。 多级的每个移位寄存器单元电路包括具有源极和漏极的第一晶体管，其中输入第一时钟信号中的一个，并且通过基本上反相第一时钟信号而获得的第二时钟信号的栅极是 输入。 当在H电平和L电平之一处的第二时钟信号被输入到第一晶体管的栅极时，H电平和L电平中的另一个处的第一时钟信号被输入到源极和漏极之一 的第一晶体管。