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12 条记录 (耗时 0.033 秒)

    NETWORK COMMUNICATION SYSTEM WITH PACKET FORWARDING AND METHOD OF OPERATION THEREOF
    5.
    发明申请
    NETWORK COMMUNICATION SYSTEM WITH PACKET FORWARDING AND METHOD OF OPERATION THEREOF 有权
    具有分组转发的网络通信系统及其操作方法

    公开(公告)号：US20120250687A1

    公开(公告)日：2012-10-04

    申请号：US13078737

    申请日：2011-04-01

    申请人： Xiaochong Cao ,  Wen Hsu ,  Jian-Jr Li ,  Chih-Hsien Hsu

    发明人： Xiaochong Cao ,  Wen Hsu ,  Jian-Jr Li ,  Chih-Hsien Hsu

    IPC分类号： H04L12/56

    CPC分类号： H04L45/02 ,  H04L45/121 ,  H04L45/7453

    摘要： A method of operation of a network communication system includes: analyzing a packet header by: loading a packet input register, generating a forwarding hash from the packet input register, and identifying a routing update by comparing the forwarding hash; accessing a packet analysis bus for updating the packet header; and enabling a routing switch for forwarding a packet including the packet header updated.

    摘要翻译： 网络通信系统的操作方法包括：通过以下方式分析分组报头：加载分组输入寄存器，从分组输入寄存器生成转发散列，以及通过比较转发散列来识别路由更新; 访问分组分析总线来更新分组报头; 以及启用用于转发包括更新的分组头的分组的路由交换机。

    Network communication system with packet forwarding and method of operation thereof
    6.
    发明授权
    Network communication system with packet forwarding and method of operation thereof 有权
    具有分组转发的网络通信系统及其操作方法

    公开(公告)号：US09088476B2

    公开(公告)日：2015-07-21

    申请号：US13078737

    申请日：2011-04-01

    申请人： Xiaochong Cao ,  Wen Hsu ,  Jian-Jr Li ,  Chih-Hsien Hsu

    发明人： Xiaochong Cao ,  Wen Hsu ,  Jian-Jr Li ,  Chih-Hsien Hsu

    IPC分类号： H04L12/751 ,  H04L12/727 ,  H04L12/743

    CPC分类号： H04L45/02 ,  H04L45/121 ,  H04L45/7453

    摘要： A method of operation of a network communication system includes: analyzing a packet header by: loading a packet input register, generating a forwarding hash from the packet input register, and identifying a routing update by comparing the forwarding hash; accessing a packet analysis bus for updating the packet header; and enabling a routing switch for forwarding a packet including the packet header updated.

    摘要翻译： 网络通信系统的操作方法包括：通过以下方式分析分组报头：加载分组输入寄存器，从分组输入寄存器生成转发散列，以及通过比较转发散列来识别路由更新; 访问分组分析总线来更新分组报头; 以及启用用于转发包括更新的分组头的分组的路由交换机。

    Thermal processing apparatus
    7.
    发明授权
    Thermal processing apparatus 失效
    热处理设备

    公开(公告)号：US5756964A

    公开(公告)日：1998-05-26

    申请号：US823363

    申请日：1997-03-24

    申请人： Chih-Hsien Hsu ,  Wen Jye Chung

    发明人： Chih-Hsien Hsu ,  Wen Jye Chung

    IPC分类号： C30B31/14 ,  H01L21/00 ,  F27B1/28 ,  F27B5/18

    CPC分类号： H01L21/67109 ,  C30B31/14

    摘要： A thermal processing apparatus for processing a wafer is disclosed. The thermal processing apparatus includes a thermal processing plate, a plurality of spacers, a plurality of locators, and a plurality of sensors. The temperature of the thermal processing plate is controlled within a predetermined range. The spacers are arranged over the thermal processing plate for supporting the wafer, thereby forming a gap between the wafer and the thermal processing plate. The locators, each of which is disposed over one of the spacers, are provided for locating the wafer. The sensors, each of which is disposed over one of the locators, are provided for detecting the position of the wafer.

    摘要翻译： 公开了一种用于处理晶片的热处理装置。 热处理装置包括热处理板，多个间隔件，多个定位器和多个传感器。 热处理板的温度控制在预定范围内。 间隔件布置在热处理板上方，用于支撑晶片，从而在晶片和热处理板之间形成间隙。 每个定位器设置在一个间隔件上，用于定位晶片。 每个传感器设置在一个定位器上，用于检测晶片的位置。

    Method of forming a layer on a semiconductor substrate having a plurality of trenches
    8.
    发明授权
    Method of forming a layer on a semiconductor substrate having a plurality of trenches 有权
    在具有多个沟槽的半导体衬底上形成层的方法

    公开(公告)号：US08673788B2

    公开(公告)日：2014-03-18

    申请号：US12845531

    申请日：2010-07-28

    申请人： Chung-Hsiu Cheng ,  Shih-Hao Wu ,  Chih-Hsien Hsu ,  Chia-Chi Chung ,  Wei-Yueh Tseng

    发明人： Chung-Hsiu Cheng ,  Shih-Hao Wu ,  Chih-Hsien Hsu ,  Chia-Chi Chung ,  Wei-Yueh Tseng

    IPC分类号： H01L21/302 ,  H01L21/461 ,  C03C25/00 ,  C23F1/00 ,  B44C1/22

    CPC分类号： H01L21/32137 ,  H01L21/31138 ,  H01L21/32115

    摘要： A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

    摘要翻译： 示出了制造半导体器件的方法。 提供具有多个沟槽的衬底。 多个沟槽包括具有不同宽度的沟槽。 在包括在多个沟槽中的衬底上形成第一层。 形成第一层在覆盖沟槽（例如，宽沟槽）的区域中的第一层中形成凹陷。 第二层形成在压痕中。 第一层被蚀刻，而第二层保留在压痕中。 第二层可以保护压痕区域进一步减小厚度。 在一个实施例中，第一层是多晶硅，第二层是光致抗蚀剂的BARC。

    METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING A PLURALITY OF TRENCHES
    9.
    发明申请
    METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING A PLURALITY OF TRENCHES 有权
    在具有多个梯度的半导体基板上形成层的方法

    公开(公告)号：US20120028468A1

    公开(公告)日：2012-02-02

    申请号：US12845531

    申请日：2010-07-28

    申请人： Chung-Hsiu Cheng ,  Shih-Hao Wu ,  Chih-Hsien Hsu ,  Chia-Chi Chung ,  Wei-Yueh Tseng

    发明人： Chung-Hsiu Cheng ,  Shih-Hao Wu ,  Chih-Hsien Hsu ,  Chia-Chi Chung ,  Wei-Yueh Tseng

    IPC分类号： H01L21/02

    CPC分类号： H01L21/32137 ,  H01L21/31138 ,  H01L21/32115

    摘要： A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

    摘要翻译： 示出了制造半导体器件的方法。 提供具有多个沟槽的衬底。 多个沟槽包括具有不同宽度的沟槽。 在包括在多个沟槽中的衬底上形成第一层。 形成第一层在覆盖沟槽（例如，宽沟槽）的区域中的第一层中形成凹陷。 第二层形成在压痕中。 第一层被蚀刻，而第二层保留在压痕中。 第二层可以保护压痕区域进一步减小厚度。 在一个实施例中，第一层是多晶硅，第二层是光致抗蚀剂的BARC。

    Dynamic time sequence control device and its method for word matching circuit
    10.
    发明申请
    Dynamic time sequence control device and its method for word matching circuit 审中-公开
    动态时序控制装置及其字符匹配电路方法

    公开(公告)号：US20070109829A1

    公开(公告)日：2007-05-17

    申请号：US11272690

    申请日：2005-11-15

    申请人： Chi-Sheng Lin ,  Chun-Ming Huang ,  Lan-Da Van ,  Nien-Hsiang Chang ,  Chun-Pin Lin ,  Chih-Hsien Hsu ,  Chau-Chin Wang

    发明人： Chi-Sheng Lin ,  Chun-Ming Huang ,  Lan-Da Van ,  Nien-Hsiang Chang ,  Chun-Pin Lin ,  Chih-Hsien Hsu ,  Chau-Chin Wang

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04

    摘要： A dynamic time sequence control device and its method for a word matching circuit. The word matching circuit includes a first switch connected between an input voltage and a node to respond to a control signal generated by a pre-charging circuit so that within a pre-charging phase period a current is generated to flow through a capacitor to generate a charging voltage. The node is connected to multiple data memories and matching circuits so that the matching result can be outputted through the node. The dynamic time sequence control device includes a second switch connected between the first switch and the node. A third switch is connected between the data memory and matching circuit and a self time sequence controller has a threshold value to respond to the control signal and to conduct the second switch and turn off the third switch during the pre-charging phase period, meanwhile, it turns off the second switch and conducts the third switch when the charging voltage is detected to be larger than threshold value. The self time sequence controller detects the output voltage of the node and outputs the data matching result during a value-acquisition phase period.

    摘要翻译： 一种动态时序控制装置及其字符匹配电路的方法。 字匹配电路包括连接在输入电压和节点之间的第一开关，以响应由预充电电路产生的控制信号，使得在预充电阶段期间内产生电流以流过电容器以产生 充电电压。 节点连接到多个数据存储器和匹配电路，以便可以通过节点输出匹配结果。 动态时序控制装置包括连接在第一开关和节点之间的第二开关。 第三开关连接在数据存储器和匹配电路之间，自适应时序控制器具有阈值以响应控制信号并导通第二开关并在预充电阶段期间关闭第三开关， 当检测到充电电压大于阈值时，它关闭第二开关并导通第三开关。 自适应时序控制器检测节点的输出电压，并在数据采集阶段期间输出数据匹配结果。