公开(公告)号：US20100295403A1

公开(公告)日：2010-11-25

申请号：US12778424

申请日：2010-05-12

申请人： Yusuke MORITA ,  Masatsugu Nakano ,  Sachiko Kawasaki

发明人： Yusuke MORITA ,  Masatsugu Nakano ,  Sachiko Kawasaki

IPC分类号： H02K1/16 ,  H02K1/27

CPC分类号： H02K1/146 ,  H02K1/223 ,  H02K21/14 ,  H02K21/16 ,  H02K29/06 ,  H02K29/12 ,  H02K2213/03

摘要： Provided is a permanent magnet type motor including: a rotor including a rotor core and a plurality of permanent magnets; a conducting circuit including a first electric conductor extending in an axial direction of the rotor and being disposed between permanent magnets in a circumferential direction of the rotor and a second electric conductor for connecting the first electric conductors electrically; and a stator disposed so as to be opposed to the rotor, including a stator core and an armature winding. A rotation angle is detected by measuring current flowing in the armature winding. The stator core is formed to have a shape in which, a slot pitch is defined by ρs=(2×π×Rs)/Ns, where an inner radius of the stator is represented by Rs and a number of slots is represented by Ns, a value Wsn obtained by dividing a slot opening width Ws by the slot pitch ρs satisfies “0.08≦Wsn”.

摘要翻译： 提供一种永磁式电动机，其包括：转子，包括转子芯和多个永磁体; 导体电路，包括沿着转子的轴向延伸并且在转子的周向上设置在永磁体之间的第一导电体和用于电连接第一电导体的第二电导体; 以及与转子相对设置的定子，包括定子芯和电枢绕组。 通过测量在电枢绕组中流动的电流来检测旋转角度。 定子铁芯的形状是这样一种形状：槽间距由＆rgr; s =（2×＆pgr;×Rs）/ Ns定义，其中定子的内半径由Rs表示，槽数为 通过用Ns表示，通过将槽开口宽度Ws除以槽间距＆rgrs而获得的值Wsn满足“0.08＆nlE; Wsn”。

公开(公告)号：US20120293752A1

公开(公告)日：2012-11-22

申请号：US13470578

申请日：2012-05-14

申请人： Arihiro TAKEDA ,  Jin HIROSAWA ,  Hitomi HASEGAWA ,  Yusuke MORITA ,  Hirokazu MORIMOTO

发明人： Arihiro TAKEDA ,  Jin HIROSAWA ,  Hitomi HASEGAWA ,  Yusuke MORITA ,  Hirokazu MORIMOTO

IPC分类号： G02F1/1343 ,  G02F1/1335 ,  G02F1/1337

CPC分类号： G02F1/134363 ,  G02F2001/134318 ,  G02F2001/134381

摘要： A liquid crystal display device includes a first substrate having a pair of first signal lines and a pair of second signal lines extending in a first and orthogonal second directions, and a pixel electrode arranged between the pair of second signal lines and extending in the second direction, and a second substrate having a first main common electrode and a second main common electrode respectively facing the pair of second signal lines and extending in the second direction. An effective domain is surrounded by the pairs of first and second signal lines, or by the pair of the first signal lines and the first and the second main common electrodes. A first area formed of an electrode portion including the pixel electrode is smaller than a second area formed of an aperture portion other than the first area in the effective domain.

摘要翻译： 液晶显示装置包括具有一对第一信号线和在第一正交的第二方向上延伸的一对第二信号线的第一基板和配置在该对第二信号线之间并在第二方向延伸的像素电极 以及具有分别面对所述一对第二信号线并沿第二方向延伸的第一主公共电极和第二主公共电极的第二基板。 有效域被第一和第二信号线对，或者由一对第一信号线和第一和第二主公共电极围绕。 由包括像素电极的电极部分形成的第一区域小于由有效区域中的第一区域以外的开口部分形成的第二区域。

公开(公告)号：US20120182509A1

公开(公告)日：2012-07-19

申请号：US13339915

申请日：2011-12-29

申请人： Keisuke TAKANO ,  Arihiro TAKEDA ,  Takashi SASABAYASHI ,  Nobuko FUKUOKA ,  Yusuke MORITA ,  Jin HIROSAWA ,  Hitomi HASEGAWA ,  Yoshitaka YAMADA ,  Keiji TAGO ,  Hirokazu MORIMOTO

发明人： Keisuke TAKANO ,  Arihiro TAKEDA ,  Takashi SASABAYASHI ,  Nobuko FUKUOKA ,  Yusuke MORITA ,  Jin HIROSAWA ,  Hitomi HASEGAWA ,  Yoshitaka YAMADA ,  Keiji TAGO ,  Hirokazu MORIMOTO

IPC分类号： G02F1/1337

CPC分类号： G02F1/134363 ,  G02F2001/133562 ,  G02F2001/133776 ,  G02F2001/134318 ,  G02F2001/134381

摘要： In one embodiment, a first substrate includes a pixel electrode having a first main electrode in a belt-like shape extending along a first cross line direction which crosses at an acute angle in a counterclockwise direction with respect to an initial alignment direction of liquid crystal molecules, and a second main electrode in the belt-like shape extending along a second cross line direction which crosses at an acute angle in a clockwise direction with respect to the initial alignment direction of the liquid crystal molecules. A second substrate includes a counter electrode having a pair of third main electrodes in the belt-like shape arranged above a pair of regions sandwiching the first main electrode extending along a first cross line direction and a pair of fourth main electrodes in the belt-like shape arranged above a pair of regions sandwiching the second main electrode extending along the second cross line direction.

摘要翻译： 在一个实施例中，第一基板包括像素电极，该像素电极具有沿着第一交叉线方向延伸的带状形状，该第一主电极相对于液晶分子的初始取向方向在逆时针方向上以锐角交叉 以及沿着相对于液晶分子的初始取向方向沿顺时针方向以锐角交叉的第二交叉方向延伸的带状的第二主电极。 第二基板包括对电极，其具有带状的一对第三主电极，该一对第三主电极布置在夹着沿着第一交叉线方向延伸的第一主电极的一对区域和带状的一对第四主电极之间 形状布置在夹着沿第二交叉线方向延伸的第二主电极的一对区域上方。

公开(公告)号：US20110195566A1

公开(公告)日：2011-08-11

申请号：US13088020

申请日：2011-04-15

申请人： Takashi ISHIGAKI ,  Ryuta TSUCHIYA ,  Yusuke MORITA ,  Nobuyuki SUGII ,  Shinichiro KIMURA ,  Toshiaki IWAMATSU

发明人： Takashi ISHIGAKI ,  Ryuta TSUCHIYA ,  Yusuke MORITA ,  Nobuyuki SUGII ,  Shinichiro KIMURA ,  Toshiaki IWAMATSU

IPC分类号： H01L21/3205

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US20100258872A1

公开(公告)日：2010-10-14

申请号：US12756451

申请日：2010-04-08

申请人： Nobuyuki SUGII ,  Ryuta TSUCHIYA ,  Shinichiro KIMURA ,  Takashi ISHIGAKI ,  Yusuke MORITA ,  Hiroyuki YOSHIMOTO

发明人： Nobuyuki SUGII ,  Ryuta TSUCHIYA ,  Shinichiro KIMURA ,  Takashi ISHIGAKI ,  Yusuke MORITA ,  Hiroyuki YOSHIMOTO

IPC分类号： H01L29/786 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/76283

摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

公开(公告)号：US20120268677A1

公开(公告)日：2012-10-25

申请号：US13454711

申请日：2012-04-24

申请人： Yusuke MORITA ,  Jin Hirosawa

发明人： Yusuke MORITA ,  Jin Hirosawa

IPC分类号： G02F1/1343

CPC分类号： G02F1/134336 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/134363 ,  G02F2001/133738 ,  G02F2001/134318 ,  G02F2001/134345

摘要： A liquid crystal display in which a first substrate includes a sub-pixel electrode extending in a first direction, and first and second main pixel electrodes connected with opposite ends of the sub-pixel electrode and extending in a second direction orthogonally crossing the first direction. A second substrate includes first and second sub-common electrodes arranged on both sides sandwiching the sub-pixel electrode, a first main common electrode connected with the first sub-common electrode and extending along the second direction opposite to the extending direction of the first main pixel electrode on one end side of the sub-pixel electrode, and a second main common electrode connected with the second sub-common electrode and extending along the second direction opposite to the extending direction of the second main pixel electrode on the other end side of the sub-pixel electrode.

摘要翻译： 一种液晶显示器，其中第一基板包括沿第一方向延伸的子像素电极，以及第一和第二主像素电极，其与子像素电极的相对端连接并且沿与第一方向正交的第二方向延伸。 第二基板包括布置在夹着子像素电极的两侧的第一和第二副公共电极，与第一副公共电极连接并且沿着与第一主公共电极的延伸方向相反的第二方向延伸的第一主公共电极 以及与第二副公共电极连接并且沿与第二主像素电极的延伸方向相反的第二方向延伸的第二主公共电极在另一端侧的子像素电极的一端侧的像素电极 子像素电极。

公开(公告)号：US20120236239A1

公开(公告)日：2012-09-20

申请号：US13348906

申请日：2012-01-12

申请人： Yusuke MORITA ,  Jin Hirosawa ,  Arihiro Takeda ,  Nobuko Fukuoka ,  Keiji Tago ,  Kazuya Daishi

发明人： Yusuke MORITA ,  Jin Hirosawa ,  Arihiro Takeda ,  Nobuko Fukuoka ,  Keiji Tago ,  Kazuya Daishi

IPC分类号： G02F1/1337

CPC分类号： G02F1/136286 ,  G02F1/1336 ,  G02F1/1337 ,  G02F1/134309 ,  G02F1/134336 ,  G02F1/1368 ,  G02F2001/133738 ,  G02F2001/134318

摘要： In one embodiment, a liquid crystal display device comprises a pixel electrode including a first main electrode disposed between a first line and a second line and extending like a belt in a first extending direction. A first counter electrode includes a second main electrode extending like a belt in the first extending direction, a second counter electrode having a third main electrode extending like a belt in the first extending direction. The second and third main electrodes are disposed on both sides of the first main electrode, and an initial alignment direction of the liquid crystal molecules is parallel with a direction passing through an interstice between the first end side of the first main electrode and the second line, and through an interstice between the second end side of the first main electrode and the first line.

摘要翻译： 在一个实施例中，液晶显示装置包括像素电极，其包括设置在第一线和第二线之间的第一主电极，并且沿第一延伸方向像带一样延伸。 第一对电极包括在第一延伸方向上像带一样延伸的第二主电极，第二对电极具有在第一延伸方向上像带一样延伸的第三主电极。 第二和第三主电极设置在第一主电极的两侧，并且液晶分子的初始取向方向与穿过第一主电极的第一端侧和第二主线之间的间隙的方向平行 并且通过第一主电极的第二端侧与第一线之间的间隙。

公开(公告)号：US20120099070A1

公开(公告)日：2012-04-26

申请号：US13242321

申请日：2011-09-23

申请人： Jin HIROSAWA ,  Arihiro TAKEDA ,  Nobuko FUKUOKA ,  Yusuke MORITA ,  Kazuya DAISHI

发明人： Jin HIROSAWA ,  Arihiro TAKEDA ,  Nobuko FUKUOKA ,  Yusuke MORITA ,  Kazuya DAISHI

IPC分类号： G02F1/1343

CPC分类号： G02F1/134309 ,  G02F1/13306 ,  G02F1/133514 ,  G02F1/133528 ,  G02F1/133784 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/133738 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/134381 ,  G02F2201/123 ,  G02F2202/28

摘要： In one embodiment, a liquid crystal display device includes a first substrate and a second substrate. In the first substrate, gate lines extend in a first direction, and a first source line and a second source line extend in a second direction orthogonally crossing the first direction. A pixel electrode having a first belt-like main electrode is arranged approximately in a central portion between the first source line and the second source line and extending in the second direction. A first belt-like sub-electrode covers the gate line between the first source line and the second source line and extending in the first direction. The second substrate includes a counter electrode having a second main electrode arranged on the first and second source lines and extending in the second direction. A liquid crystal layer is held between the first substrate and the second substrate.

摘要翻译： 在一个实施例中，液晶显示装置包括第一基板和第二基板。 在第一衬底中，栅极线在第一方向上延伸，并且第一源极线和第二源极线在与第一方向正交的第二方向上延伸。 具有第一带状主电极的像素电极大致布置在第一源极线和第二源极线之间的中心部分中并沿第二方向延伸。 第一带状子电极覆盖第一源极线和第二源极线之间的栅极线并沿第一方向延伸。 第二基板包括具有布置在第一和第二源极线上并沿第二方向延伸的第二主电极的对电极。 液晶层保持在第一基板和第二基板之间。

公开(公告)号：US20130242216A1

公开(公告)日：2013-09-19

申请号：US13749950

申请日：2013-01-25

申请人： Yusuke MORITA ,  Jin HIROSAWA ,  Hitomi HASEGAWA

发明人： Yusuke MORITA ,  Jin HIROSAWA ,  Hitomi HASEGAWA

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F1/133753 ,  G02F1/134336 ,  G02F2202/42

摘要： In one embodiment, a first substrate includes a gate line extending in a first direction, a source line extending in a second direction orthogonally crossing the first direction, a sub-pixel electrode extending in the first direction, and a pixel electrode having “n” main pixel electrodes electrically connected with the sub-pixel electrode and extending in the second direction (“n” is positive integer). A second substrate includes a main common electrode extending in the second direction in parallel with the “n” main pixel electrodes, and a liquid crystal layer held between the first and second substrates and including liquid crystal molecules. The dielectric constant anisotropy Δ∈ of the liquid crystal molecules satisfies a following relational expression with respect to a definition depending on an inter-electrode distance between the main pixel electrode and the main common electrode in the first direction. Δ∈≧−0.014×(definition)+(19.7−4(n−1))

摘要翻译： 在一个实施例中，第一基板包括沿第一方向延伸的栅极线，沿与第一方向正交的第二方向延伸的源极线，沿第一方向延伸的子像素电极和具有“n”的像素电极， 主像素电极与子像素电极电连接并沿第二方向延伸（“n”为正整数）。 第二基板包括在第二方向上与“n”个主像素电极平行地延伸的主公共电极以及保持在第一和第二基板之间并包括液晶分子的液晶层。 液晶分子的介电常数各向异性DeltaE相对于根据第一方向上的主像素电极和主公共电极之间的电极间距离的定义而满足以下关系式。 DeltaE> = - 0.014×（定义）+（19.7-4（n-1））

公开(公告)号：US20100258869A1

公开(公告)日：2010-10-14

申请号：US12757090

申请日：2010-04-09

申请人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).

摘要翻译： 形成在具有薄BOX层的SOI衬底的主表面上以预定间隔布置的n阱和p阱，并且在p阱上形成的nMIS具有形成在半导体层上的一对n型源极/漏极区 堆叠在SOI层的主表面上，预定距离处，栅极绝缘膜，栅电极和夹在该对n型源极/漏极区之间的侧壁。 在n阱和p阱之间形成器件隔离，并且器件隔离的侧边缘部分比n型源极/漏极区域的侧边缘部分（BOX层的侧壁）朝向栅电极侧延伸 ）。