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    Forced air cooling apparatus having blower and air current regulating plate that reduces eddy air current at inlet of blower
    1.
    发明授权
    Forced air cooling apparatus having blower and air current regulating plate that reduces eddy air current at inlet of blower 失效
    具有鼓风机和气流调节板的强制空气冷却装置可减少鼓风机入口的涡流

    公开(公告)号：US5558493A

    公开(公告)日：1996-09-24

    申请号：US477653

    申请日：1995-06-07

    申请人： Yutaka Hayashi ,  Mitsuo Miyamoto ,  Michihito Watarai ,  Takayuki Atarashi ,  Tetsuya Tanaka ,  Toshio Hatada ,  Yoshihiro Takada ,  Takahiro Daikoku

    发明人： Yutaka Hayashi ,  Mitsuo Miyamoto ,  Michihito Watarai ,  Takayuki Atarashi ,  Tetsuya Tanaka ,  Toshio Hatada ,  Yoshihiro Takada ,  Takahiro Daikoku

    IPC分类号： F25D1/00 ,  C04B28/18 ,  F04D29/42 ,  H05K7/20 ,  F04D29/66

    CPC分类号： F04D29/4213

    摘要： A forced air cooling apparatus having a blower for blowing air taken in from an intake surface or inlet of the blower to be blown against an electronic device in an installation wherein the blower is mounted for operation on a casing or a rack, and in which the apparatus has a flow regulating plate vertically intersecting the intake surface that is installed immediately before the intake surface. With this construction, eddy air current flow in the vicinity of the intake surface is prevented and the cooling ability obtained from the blower is optimized to thereby attain the effect that the electronic devices can be efficiently cooled without requiring the same separation distance between an intake surface of the blower and a wall surface of the frame or casing in which the blower is installed, as compared with a conventional installation of the same equipment in the same casing without the flow regulating plate.

    摘要翻译： 一种强制用空气冷却装置，其特征在于，具有鼓风机，所述鼓风机用于将鼓风机从壳体或机架上进行操作的设备中，从鼓风机的进气表面或进气口吸入的空气吹向电子设备，其中， 装置具有垂直于入口表面垂直相交的流动调节板，其紧靠在进气表面之前安装。 通过这种结构，可以防止在进气表面附近的涡流流动，从鼓风机获得的冷却能力最优化，从而达到能够有效地冷却电子设备的效果，而不需要在进气表面 的鼓风机和安装有鼓风机的框架或壳体的壁面相比，与同一设备的常规安装相比，在没有流量调节板的情况下。

    Mounting structure for electronic device
    2.
    发明授权
    Mounting structure for electronic device 失效
    电子设备的安装结构

    公开(公告)号：US06285546B1

    公开(公告)日：2001-09-04

    申请号：US09450380

    申请日：1999-11-29

    申请人： Michihito Watarai ,  Yutaka Hayashi ,  Mitsuo Miyamoto ,  Kazuhiro Matsuo ,  Eiji Kadomoto ,  Koji Nakayama ,  Akihiro Sakurai ,  Shigeyasu Tsubaki

    发明人： Michihito Watarai ,  Yutaka Hayashi ,  Mitsuo Miyamoto ,  Kazuhiro Matsuo ,  Eiji Kadomoto ,  Koji Nakayama ,  Akihiro Sakurai ,  Shigeyasu Tsubaki

    IPC分类号： H05K720

    CPC分类号： H05K7/20736

    摘要： An electronic device has a frame and a back board having plural logical units and power supply units mounted thereon. The logical units and the power supply units are alternately located on both sides of the back board in the center of the frame so that the power supply units mounted on one side of the back board may feed a power to the closest logical units mounted on the other side. Further, the air flow paths to be circulated through the logical units and the power supply units are formed so that each unit may be efficiently cooled by the air fed by an air fan unit. As a result, the feeding voltage becomes uniform and the cooling efficiency is improved.

    摘要翻译： 电子设备具有框架和背板，其具有多个逻辑单元和安装在其上的电源单元。 逻辑单元和电源单元交替地位于框架中心的背板的两侧，使得安装在背板的一侧上的电源单元可以将电力馈送到安装在背板上的最接近的逻辑单元 另一边。 此外，通过逻辑单元和电源单元循环的空气流动路径被形成为使得每个单元可以被由空气风扇单元供给的空气有效地冷却。 结果，供电电压变得均匀，并且提高了冷却效率。

    Field effect transistor formed on an insulating substrate and integrated circuit thereof
    5.
    发明授权
    Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权

    公开(公告)号：US08450799B2

    公开(公告)日：2013-05-28

    申请号：US11975923

    申请日：2007-10-22

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

    IPC分类号： H01L29/34

    CPC分类号： H01L29/78615 ,  H01L29/66772

    摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

    Memory cell array
    6.
    发明授权
    Memory cell array 有权
    存储单元阵列

    公开(公告)号：US08094484B2

    公开(公告)日：2012-01-10

    申请号：US12644851

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C11/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取 放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和 门极阈值电压以下。

    MEMORY DEVICE AND READING METHOD THEREOF
    7.
    发明申请
    MEMORY DEVICE AND READING METHOD THEREOF 有权
    存储器件及其读取方法

    公开(公告)号：US20100208522A1

    公开(公告)日：2010-08-19

    申请号：US12601788

    申请日：2008-05-23

    申请人： Yutaka Hayashi ,  Kazuhika Matsumoto ,  Takafumi Kamimura

    发明人： Yutaka Hayashi ,  Kazuhika Matsumoto ,  Takafumi Kamimura

    IPC分类号： G11C16/02 ,  H01L27/105

    CPC分类号： H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/0657 ,  H01L29/1606 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/7781 ,  H01L29/792

    摘要： A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.

    摘要翻译： 存储器件（1）至少包括具有由第一表面包围的长度，第一表面和横截面的第一半导体区域（100），设置在第一表面上的存储器件（300）和栅极 400），并且将第一半导体区域（100）的横截面的等效截面半径设定为等于或小于存储装置（300）的等效氧化硅膜厚度， 实现低编程电压。 横截面的等效截面半径r设定为10nm以下，栅极长度设定为20nm以下，使得转换为栅极电压的多级间隔成为能够在室内识别的特定值 温度。

    Memory Cell Array
    8.
    发明申请
    Memory Cell Array 有权
    存储单元阵列

    公开(公告)号：US20100165696A1

    公开(公告)日：2010-07-01

    申请号：US12644608

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C5/06 ,  G11C7/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线 以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线 或更少。

    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof
    9.
    发明授权
    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof 有权
    高电压工作场效应晶体管，其偏置电路及其高电压电路

    公开(公告)号：US07545018B2

    公开(公告)日：2009-06-09

    申请号：US11063388

    申请日：2005-02-22

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

    摘要： A high voltage operating field effect transistor has a substrate, a source region and a drain region which are spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region. At least one of a signal electric potential and a signal current is supplied to the source region, and a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential is supplied to the gate region. One end of a rectifying device is connected to the gate region, and a second constant electric potential is supplied to the other end of the rectifying device.

    摘要翻译： 高电压工作场效应晶体管具有在基板的表面上彼此间隔开的基板，源极区域和漏极区域，设置在基板的表面中的源极区域与源极区域之间的半导体沟道形成区域， 漏极区域，设置在沟道形成区域上方的栅极区域和设置在沟道形成区域和栅极区域之间的栅极绝缘膜区域。 将信号电位和信号电流中的至少一个提供给源极区域，并且具有绝对值等于或大于根据漏极电流的增减的第一恒定电位变化的偏置电位 电位被提供给栅极区域。 整流装置的一端与栅极区域连接，第二恒定电位被提供给整流装置的另一端。

    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof
    10.
    发明申请
    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof 有权
    高电压工作场效应晶体管，其偏置电路及其高电压电路

    公开(公告)号：US20090014765A1

    公开(公告)日：2009-01-15

    申请号：US12283639

    申请日：2008-09-12

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    IPC分类号： H03K5/08 ,  H01L27/06

    CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

    摘要： A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

    摘要翻译： 高电压工作场效应晶体管具有在衬底的表面中彼此间隔开的源极区和漏极区。 源区域可操作以接收信号电位和信号电流中的至少一个。 半导体沟道形成区域设置在源极区域和漏极区域之间的衬底的表面中。 栅极区域设置在沟道形成区域上方，并且可操作以接收具有等于或大于根据漏极电位的增加或减小而改变的第一恒定电位的绝对值的偏置电位。 栅极绝缘膜区域设置在沟道形成区域和栅极区域之间。