公开(公告)号：US07910464B2

公开(公告)日：2011-03-22

申请号：US12695759

申请日：2010-01-28

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/66871 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/8128

摘要： A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.

摘要翻译： 本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。 深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

公开(公告)号：US20090050937A1

公开(公告)日：2009-02-26

申请号：US12257807

申请日：2008-10-24

申请人： Tomohiro MURATA ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

发明人： Tomohiro MURATA ,  Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC分类号： H01L29/778

CPC分类号： H01L29/66871 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/8128

摘要： A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.

摘要翻译： 本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。 深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

公开(公告)号：US07339207B2

公开(公告)日：2008-03-04

申请号：US11455631

申请日：2006-06-20

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L31/0328

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电衬底上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N构成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。

公开(公告)号：US07217960B2

公开(公告)日：2007-05-15

申请号：US11325340

申请日：2006-01-05

申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L33/00

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小 可以实现。

公开(公告)号：US07187014B2

公开(公告)日：2007-03-06

申请号：US10862452

申请日：2004-06-08

申请人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

发明人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

IPC分类号： H01L29/772

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

摘要翻译： 半导体器件具有蓝宝石衬底，设置在蓝宝石衬底上的由GaN制成的半导体层，设置在半导体层上的多层膜和与该多层膜欧姆接触的电极。 已经通过交替地堆叠具有不同量的极化或不同量的自发极化的两种类型的半导体层，并且每个含有n型杂质，以便在两种类型的半导体层之间的界面处诱导电子而形成多层膜。 这允许电极和多层膜之间的接触电阻和电流传输路径中的寄生电阻降低到比常规半导体器件中的值更低的值。

公开(公告)号：US07528423B2

公开(公告)日：2009-05-05

申请号：US11681408

申请日：2007-03-02

申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度 可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。 因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

公开(公告)号：US20070210332A1

公开(公告)日：2007-09-13

申请号：US11681408

申请日：2007-03-02

申请人： Hiroaki UENO ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki UENO ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L31/00

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小 可以实现。

公开(公告)号：US20060284318A1

公开(公告)日：2006-12-21

申请号：US11436722

申请日：2006-05-19

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L23/52

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

摘要： According to a method for fabricating a semiconductor device, a first semiconductor layer made of a first nitride semiconductor is formed over a substrate. Thereafter, a mask film covering part of the upper surface of the first semiconductor layer is selectively formed on the first semiconductor layer. A multilayer film, in which second and third nitride semiconductors having different band gaps are stacked, is selectively formed on the first semiconductor layer with the mask film used as a formation mask. On the multilayer film, an ohmic electrode is formed.

摘要翻译： 根据半导体器件的制造方法，在基板上形成由第一氮化物半导体构成的第一半导体层。 此后，在第一半导体层上选择性地形成覆盖第一半导体层的上表面的一部分的掩模膜。 选择性地在第一半导体层上形成具有不同带隙的第二和第三氮化物半导体的多层膜，其中掩模膜用作形成掩模。 在多层膜上形成欧姆电极。

公开(公告)号：US20060157729A1

公开(公告)日：2006-07-20

申请号：US11325340

申请日：2006-01-05

申请人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

发明人： Hiroaki Ueno ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Manabu Yanagihara ,  Yutaka Hirose ,  Masahiro Hikita

IPC分类号： H01L33/00

CPC分类号： H01L29/7786 ,  H01L29/2003

摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.

摘要翻译： 本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善 和栅极漏电流的减小。 为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max， 配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。 因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。 介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低 可以实现。

公开(公告)号：US07078743B2

公开(公告)日：2006-07-18

申请号：US10834362

申请日：2004-04-29

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L31/0328

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电基板上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。