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    SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
    1.
    发明申请
    SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 有权
    用于金属高K介电金属绝缘体金属（MIM）嵌入式动态随机存取存储器的自对准底板

    公开(公告)号：US20130062677A1

    公开(公告)日：2013-03-14

    申请号：US13228767

    申请日：2011-09-09

    申请人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

    发明人： Zhengwen Li ,  Damon B. Farmer ,  Michael P. Chudzik ,  Keith Kwong Hon Wong ,  Jian Yu ,  Zhen Zhang ,  Chengwen Pei

    IPC分类号： H01L21/20 ,  H01L27/06

    CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/945

    摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

    摘要翻译： 提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。 在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。 电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层 金属电极。 存储器件还包括与电容器电连通的传输晶体管。

    STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL
    5.
    发明申请
    STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL 有权
    结构和方法替代金属门和接触金属

    公开(公告)号：US20120187420A1

    公开(公告)日：2012-07-26

    申请号：US13427963

    申请日：2012-03-23

    申请人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

    发明人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/16 ,  H01L29/78

    CPC分类号： H01L23/485 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76283 ,  H01L21/76877 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

    摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和 铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。 层间电介质存在于半导体衬底上。 层间电介质包括到p型和n型半导体器件的源区和漏区的互连。 互连由钛和铝构成的金属层和由铝组成的金属填充物构成。 本公开还提供了形成上述结构的方法。

    Structure and method to make replacement metal gate and contact metal
    7.
    发明授权
    Structure and method to make replacement metal gate and contact metal 有权
    用于替换金属栅极和接触金属的结构和方法

    公开(公告)号：US08552502B2

    公开(公告)日：2013-10-08

    申请号：US13427963

    申请日：2012-03-23

    申请人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

    发明人： Zhengwen Li ,  Michael P. Chudzik ,  Unoh Kwon ,  Filippos Papadatos ,  Andrew H. Simon ,  Keith Kwong Hon Wong

    IPC分类号： H01L27/12

    CPC分类号： H01L23/485 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76283 ,  H01L21/76877 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

    摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有第一栅极结构的p型半导体器件，该第一栅极结构包括存在于半导体衬底上的栅极电介质，p型功函数金属层，由钛构成的金属层和 铝和由铝构成的金属填充物。 n型半导体器件也存在于半导体衬底上，该半导体衬底包括第二栅极结构，其包括栅极电介质，由钛和铝构成的金属层以及由铝组成的金属填充物。 层间电介质存在于半导体衬底上。 层间电介质包括到p型和n型半导体器件的源区和漏区的互连。 互连由钛和铝构成的金属层和由铝组成的金属填充物构成。 本公开还提供了形成上述结构的方法。

    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
    9.
    发明申请
    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT 有权
    具有降低闸门泄漏电流的更换门

    公开(公告)号：US20120181630A1

    公开(公告)日：2012-07-19

    申请号：US13006656

    申请日：2011-01-14

    申请人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

    摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

    摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。