公开(公告)号：US06737333B2

公开(公告)日：2004-05-18

申请号：US10176383

申请日：2002-06-20

申请人： Zhihao Chen ,  Douglas T. Grider ,  Freidoon Mehrad

发明人： Zhihao Chen ,  Douglas T. Grider ,  Freidoon Mehrad

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

摘要翻译： 隔离半导体器件的方法包括从半导体衬底向外形成第一氧化物层，从第一氧化物层向外形成第一氮化物层，去除第一氮化物层的一部分，第一氧化物层的一部分，以及部分 以形成沟槽隔离区域，在沟槽隔离区域中形成第二氧化物层，在沟槽隔离区域中形成旋涂玻璃区域，退火玻璃转移区域，去除部分旋转 以暴露浅沟槽隔离区域，并且在浅沟槽隔离区域中形成第三氧化物层。

公开(公告)号：US20050208732A1

公开(公告)日：2005-09-22

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US06828213B2

公开(公告)日：2004-12-07

申请号：US10376021

申请日：2003-02-28

申请人： Freidoon Mehrad ,  Zhihao Chen ,  Majid M. Mansoori

发明人： Freidoon Mehrad ,  Zhihao Chen ,  Majid M. Mansoori

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

摘要翻译： 通过生长衬垫氧化物，在衬垫氧化物上沉积氮化物层的步骤和护壁护理图案，护壁蚀刻和护城河清洁的步骤之后，提供了改善浅沟槽隔离（STI）间隙填充和齿隙氮化物拉回的方法， 生长热氧化物的步骤，使一部分护环氮化物脱气; 沉积薄氮化物衬垫，蚀刻氮化物以在STI沟槽中形成薄的侧壁氮化物; 并在STI衬垫氧化和沉积氧化物以填充沟槽之前进行氧化物氢氟酸（HF）酸蒸气。

公开(公告)号：US06524930B1

公开(公告)日：2003-02-25

申请号：US10131958

申请日：2002-04-25

申请人： Christoph A. Wasshuber ,  Zhihao Chen ,  Freidoon Mehrad

发明人： Christoph A. Wasshuber ,  Zhihao Chen ,  Freidoon Mehrad

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded after trench formation using an oxidation process which oxidizes substrate material from the trench sidewalls and bottom faster than from the lower corners of the trench. The oxide formed during the rounding process is then removed prior to performing other etch processes, to expose substrate material having rounded lower corners. Thereafter, a liner is formed and the trench is filled with dielectric material to complete the isolation structure.

摘要翻译： 公开了用于在半导体器件中形成隔离结构和沟槽的方法，其中隔离沟槽的下角在沟槽形成之后被圆化，使用氧化工艺，其从衬底材料从沟槽侧壁氧化衬底，并且底部比从 沟。 然后在进行其它蚀刻工艺之前去除在舍入过程中形成的氧化物，以露出具有圆形下角的衬底材料。 此后，形成衬垫，并且用电介质材料填充沟槽以完成隔离结构。

公开(公告)号：US20050247994A1

公开(公告)日：2005-11-10

申请号：US11178935

申请日：2005-07-11

申请人： Freidoon Mehrad ,  Zhihao Chen ,  Shashank Ekbote ,  Brian Trentman

发明人： Freidoon Mehrad ,  Zhihao Chen ,  Shashank Ekbote ,  Brian Trentman

IPC分类号： H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76224

摘要： Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

公开(公告)号：US20050062127A1

公开(公告)日：2005-03-24

申请号：US10691843

申请日：2003-10-23

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US06566200B2

公开(公告)日：2003-05-20

申请号：US10176139

申请日：2002-06-20

申请人： Freidoon Mehrad ,  Suresh Potla ,  Zhihao Chen

发明人： Freidoon Mehrad ,  Suresh Potla ,  Zhihao Chen

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.

公开(公告)号：US07504339B2

公开(公告)日：2009-03-17

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

IPC分类号： H01L21/311

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

摘要翻译： 描述半导体材料晶片中的沟槽结构和形成沟槽结构的方法。 沟槽结构形成在半导体晶片上，该半导体晶片具有比半导体材料的其它主要晶面平缓的氧化速度慢的顶表面。 沟槽被蚀刻到半导体晶片中。 沟槽在顶表面附近具有基本垂直的沟槽侧壁，靠近顶表面的垂直沟槽侧壁含有以与顶表面相当的速率氧化的结晶平面。 绝缘层生长在顶表面和沟槽侧壁以及侧壁表面接近顶表面的拐角处，角部处的绝缘层基本上比邻近角部的侧壁厚。 氧化物厚度的差异是由于在拐角处暴露的氧化面更快。 最后，沟槽填充有电介质材料。

公开(公告)号：US06930018B2

公开(公告)日：2005-08-16

申请号：US10196089

申请日：2002-07-16

申请人： Freidoon Mehrad ,  Zhihao Chen ,  Shashank S. Ekbote ,  Brian Trentman

发明人： Freidoon Mehrad ,  Zhihao Chen ,  Shashank S. Ekbote ,  Brian Trentman

IPC分类号： H01L21/762 ,  H01L21/8222

CPC分类号： H01L21/76224

摘要： Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

摘要翻译： 公开了一种浅沟槽隔离（STI）结构及其制造方法。 该方法消除了在制造STI结构时设计尺寸调整（DSA）的要求。 进一步公开了一种STI沟槽衬垫及其形成方法，其通过在浅隔离沟槽表面上生长薄氧化物层，同时防止在相邻的氮化物表面上形成氧化物，随后在多晶硅层上沉积和氧化物生长。

公开(公告)号：US06917093B2

公开(公告)日：2005-07-12

申请号：US10691843

申请日：2003-10-23

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

摘要翻译： 描述半导体材料晶片中的沟槽结构和形成沟槽结构的方法。 沟槽结构形成在半导体晶片上，该半导体晶片具有比半导体材料的其它主要晶面平缓的氧化速度慢的顶表面。 沟槽被蚀刻到半导体晶片中。 沟槽在顶表面附近具有基本垂直的沟槽侧壁，靠近顶表面的垂直沟槽侧壁含有以与顶表面相当的速率氧化的结晶平面。 绝缘层生长在顶表面和沟槽侧壁以及侧壁表面接近顶表面的拐角处，角部处的绝缘层基本上比邻近角部的侧壁厚。 氧化物厚度的差异是由于在拐角处暴露的氧化面更快。 最后，沟槽填充有电介质材料。