公开(公告)号：US07504339B2

公开(公告)日：2009-03-17

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

IPC分类号： H01L21/311

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

摘要翻译： 描述半导体材料晶片中的沟槽结构和形成沟槽结构的方法。 沟槽结构形成在半导体晶片上，该半导体晶片具有比半导体材料的其它主要晶面平缓的氧化速度慢的顶表面。 沟槽被蚀刻到半导体晶片中。 沟槽在顶表面附近具有基本垂直的沟槽侧壁，靠近顶表面的垂直沟槽侧壁含有以与顶表面相当的速率氧化的结晶平面。 绝缘层生长在顶表面和沟槽侧壁以及侧壁表面接近顶表面的拐角处，角部处的绝缘层基本上比邻近角部的侧壁厚。 氧化物厚度的差异是由于在拐角处暴露的氧化面更快。 最后，沟槽填充有电介质材料。

公开(公告)号：US06917093B2

公开(公告)日：2005-07-12

申请号：US10691843

申请日：2003-10-23

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian K. Kirkpatrick ,  Jeff A. White ,  Edmund G. Russell ,  Jon Holt ,  Jason D. Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

摘要翻译： 描述半导体材料晶片中的沟槽结构和形成沟槽结构的方法。 沟槽结构形成在半导体晶片上，该半导体晶片具有比半导体材料的其它主要晶面平缓的氧化速度慢的顶表面。 沟槽被蚀刻到半导体晶片中。 沟槽在顶表面附近具有基本垂直的沟槽侧壁，靠近顶表面的垂直沟槽侧壁含有以与顶表面相当的速率氧化的结晶平面。 绝缘层生长在顶表面和沟槽侧壁以及侧壁表面接近顶表面的拐角处，角部处的绝缘层基本上比邻近角部的侧壁厚。 氧化物厚度的差异是由于在拐角处暴露的氧化面更快。 最后，沟槽填充有电介质材料。

公开(公告)号：US20050208732A1

公开(公告)日：2005-09-22

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US20050062127A1

公开(公告)日：2005-03-24

申请号：US10691843

申请日：2003-10-23

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US06869862B2

公开(公告)日：2005-03-22

申请号：US10637288

申请日：2003-08-08

申请人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01I21/46 ,  H01L21/479 ,  H01I21/326 ,  H01I21/78

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。

公开(公告)号：US07531464B2

公开(公告)日：2009-05-12

申请号：US11313202

申请日：2005-12-20

申请人： Jeff White ,  Jon Holt

发明人： Jeff White ,  Jon Holt

IPC分类号： H01L21/302

CPC分类号： H01L21/31662 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/76224

摘要： The invention provides a method of fabricating a semiconductive device. In one aspect, the method comprises heating a gas mixture [225] comprising chlorohydrocarbon having a general formula of CxHxClx, wherein x=2, 3, or 4. The chlorohydrocarbon is heated in a first chamber 210 to a first temperature that substantially disassociates the chlorohydrocarbon. The substantially disassociated chlorohydrocarbon is used to form a film on a semiconductive substrate [235] that is located in a second chamber [215].

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个方面，该方法包括加热包含具有通式C x H x Cl x的氯代烃的气体混合物[225]，其中x = 2,3或4.氯代烃在第一室210中被加热至基本上分解 氯代烃。 基本上分解的氯代烃被用于在位于第二室[215]中的半导体衬底[235]上形成膜。

公开(公告)号：US20090246970A1

公开(公告)日：2009-10-01

申请号：US12424029

申请日：2009-04-15

申请人： Jeff White ,  Jon Holt

发明人： Jeff White ,  Jon Holt

IPC分类号： H01L21/302

CPC分类号： H01L21/31662 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/76224

摘要： The invention provides a method of fabricating a semiconductor device. In one aspect, the method comprises heating a gas mixture comprising chlorohydrocarbon having a general formula of CxHxClx, wherein x=2, 3, or 4, by passing it through a first chamber packed with surface area expanding members heated to a temperature to substantially dissociate the chlorohydrocarbon into chlorine and hydrocarbon. The dissociated chlorohydrocarbon is then passed, together with oxygen, into a second chamber heated to a lesser temperature to form an oxide film on a semiconductor substrate.

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个方面，该方法包括加热包含具有通式C x H x Cl x（其中x = 2,3或4）的氯代烃的气体混合物，其中x = 2,3或4通过使其通过加热到基本上解离的温度的表面积扩展构件的第一室 氯代烃成为氯和烃。 然后将解离的氯代烃与氧一起通入加热到较低温度的第二室中，以在半导体衬底上形成氧化膜。

公开(公告)号：US20070141853A1

公开(公告)日：2007-06-21

申请号：US11313202

申请日：2005-12-20

申请人： Jeff White ,  Jon Holt

发明人： Jeff White ,  Jon Holt

IPC分类号： H01L21/31

CPC分类号： H01L21/31662 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/76224

摘要： The invention provides a method of fabricating a semiconductive device. In one aspect, the method comprises heating a gas mixture [225] comprising chlorohydrocarbon having a general formula of CxHxClx, wherein x=2, 3, or 4. The chlorohydrocarbon is heated in a first chamber 210 to a first temperature that substantially disassociates the chlorohydro-carbon. The substantially disassociated chlorohydrocarbon is used to form a film on a semiconductive substrate [235] that is located in a second chamber [215].

摘要翻译： 本发明提供一种制造半导体器件的方法。 一方面，该方法包括加热含有通式为C x H x H x C x x x x的氯代烃的气体混合物[225]，其中 x = 2,3或4.将氯代烃在第一室210中加热至基本上分离氯代烃的第一温度。 基本上分解的氯代烃被用于在位于第二室[215]中的半导体衬底[235]上形成膜。

公开(公告)号：US20050156286A1

公开(公告)日：2005-07-21

申请号：US11038545

申请日：2005-01-18

申请人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/477 ,  H01L23/58

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。