公开(公告)号：US06930018B2

公开(公告)日：2005-08-16

申请号：US10196089

申请日：2002-07-16

申请人： Freidoon Mehrad ,  Zhihao Chen ,  Shashank S. Ekbote ,  Brian Trentman

发明人： Freidoon Mehrad ,  Zhihao Chen ,  Shashank S. Ekbote ,  Brian Trentman

IPC分类号： H01L21/762 ,  H01L21/8222

CPC分类号： H01L21/76224

摘要： Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

摘要翻译： 公开了一种浅沟槽隔离（STI）结构及其制造方法。 该方法消除了在制造STI结构时设计尺寸调整（DSA）的要求。 进一步公开了一种STI沟槽衬垫及其形成方法，其通过在浅隔离沟槽表面上生长薄氧化物层，同时防止在相邻的氮化物表面上形成氧化物，随后在多晶硅层上沉积和氧化物生长。

公开(公告)号：US06706605B1

公开(公告)日：2004-03-16

申请号：US10403065

申请日：2003-03-31

申请人： Shashank S. Ekbote ,  Freidoon Mehrad

发明人： Shashank S. Ekbote ,  Freidoon Mehrad

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method of forming an integrated circuit transistor (80), comprising providing a semiconductor region (90) and forming a gate structure (92, 94) in a fixed position relative to the semiconductor region. The gate structure has a first sidewall (94a) and a second sidewall (94b). The method also comprises first, forming a first layer (96) adjacent the first sidewall and the second sidewall, and second, forming a second layer (98) adjacent the first layer. The method also comprises third, forming a third layer (100) adjacent the second layer, and fourth, forming a fourth layer (102) adjacent the third layer. The method also comprises fifth, implanting a first and second source/drain region (106a, 106b) in the semiconductor region and at a first distance laterally with respect to the gate structure, wherein a combined thickness of the first, second, third, and fourth layers determines the first distance. The method also comprises sixth, removing the third and fourth layers, and seventh, implanting a third and fourth source/drain region (108a, 108b) in the semiconductor region and at a second distance laterally with respect to the gate structure, wherein the second distance is less than the first distance.

摘要翻译： 一种形成集成电路晶体管（80）的方法，包括提供半导体区域（90）并形成相对于半导体区域固定位置的栅极结构（92,94）。 栅极结构具有第一侧壁（94a）和第二侧壁（94b）。 该方法还包括首先形成邻近第一侧壁和第二侧壁的第一层（96），其次形成邻近第一层的第二层（98）。 该方法还包括第三，形成与第二层相邻的第三层（100），第四层形成与第三层相邻的第四层（102）。 该方法还包括第五步，在半导体区域中以相对于栅极结构横向第一距离注入第一和第二源/漏区（106a，106b），其中第一，第二，第三和第 第四层确定第一距离。 该方法还包括第六层，去除第三层和第四层，以及第七层，在半导体区域和相对于栅极结构的横向第二距离处注入第三和第四源/漏区（108a，108b），其中第二 距离小于第一距离。

公开(公告)号：US07994009B2

公开(公告)日：2011-08-09

申请号：US12492743

申请日：2009-06-26

申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

IPC分类号： H01L21/8234

CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。

公开(公告)号：US07572716B2

公开(公告)日：2009-08-11

申请号：US11739981

申请日：2007-04-25

申请人： Haowen Bu ,  Shashank S. Ekbote ,  Borna Obradovic ,  Srinivasan Chakravarthi

发明人： Haowen Bu ,  Shashank S. Ekbote ,  Borna Obradovic ,  Srinivasan Chakravarthi

IPC分类号： H01L21/425

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/324

摘要： A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal. The disclosure also pertains to semiconductor components produced in this manner, and various embodiments and improvements of such methods for producing such components.

摘要翻译： 公开了一种用于将诸如晶体管的源极或漏极区域的半导体衬底的目标区域掺杂到电子有源掺杂剂（例如用于在NMOS器件中产生有源区域的N型掺杂剂）或P 用于在PMOS器件中产生有源区）的具有良好控制的放置曲线和强激活。 该方法包括将目标区域中的含碳扩散抑制剂置于掺杂剂浓度的约50％处，并使掺杂剂活化约1,040摄氏度的热退火。 在许多情况下，在这样高的温度下的热退火引起掺杂剂离开目标区域的过度扩散，但这种相对浓度的碳在这样的高温热退火期间产生了掺杂剂扩散的意外的减少。 本公开还涉及以这种方式制造的半导体部件，以及用于制造这种部件的这种方法的各种实施例和改进。

公开(公告)号：US08748256B2

公开(公告)日：2014-06-10

申请号：US13366903

申请日：2012-02-06

申请人： Song Zhao ,  Gregory Charles Baldwin ,  Shashank S. Ekbote ,  Youn Sung Choi

发明人： Song Zhao ,  Gregory Charles Baldwin ,  Shashank S. Ekbote ,  Youn Sung Choi

IPC分类号： H01L27/088

CPC分类号： H01L27/0629

摘要： A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

摘要翻译： 一种形成包括硅化物阻挡多晶硅电阻（SIBLK聚电阻）的集成电路（IC）的方法包括在衬底的顶部半导体表面中形成介电隔离区。 形成多晶硅层，其包括在电介质隔离区域上的图案化电阻多晶硅和顶部半导体表面上的栅极多晶硅。 使用第一共享金属氧化物半导体（MOS）/电阻器多晶硅注入电平进行植入，以同时用至少第一掺杂剂注入MOS图案化的多晶硅和栅极多晶硅。 然后使用第二共享MOS /电阻器多晶硅注入电平进行植入，以同时用至少第二掺杂剂注入MOS图案化电阻器多晶硅，栅极多晶硅以及MOS晶体管的源极和漏极区域。 金属硅化物形成在图案化电阻器多晶硅的顶表面的第一和第二部分上以形成SIBLK多晶硅电阻器。

公开(公告)号：US07790561B2

公开(公告)日：2010-09-07

申请号：US11173088

申请日：2005-07-01

申请人： Richard P. Rouse ,  Shashank S. Ekbote ,  Haowen Bu

发明人： Richard P. Rouse ,  Shashank S. Ekbote ,  Haowen Bu

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.

摘要翻译： 本发明提供一种制造半导体器件的方法，半导体器件以及包括半导体器件的集成电路的制造方法。 制造半导体器件的方法，但不限于，可以包括在衬底（310）上方提供栅极电介质层（413,423）和栅极电极层（418,428），并且形成栅极侧壁间隔物 ），使用等离子体增强化学气相沉积工艺在栅极电介质层（413,423）和栅极电极层（418,428）的一个或多个侧壁上形成，并且在NMOS和PMOS侧壁间隔物（610,630）中形成不同的氢浓度 ）使用局部氢处理（LHT）方法。

公开(公告)号：US20090029516A1

公开(公告)日：2009-01-29

申请号：US11829181

申请日：2007-07-27

申请人： Borna Obradovic ,  Shashank S. Ekbote

发明人： Borna Obradovic ,  Shashank S. Ekbote

IPC分类号： H01L21/336

CPC分类号： H01L21/28035 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.

摘要翻译： 形成集成电路的方法包括在半导体本体上形成栅极结构，并且在半导体本体上与栅极结构横向间隔开形成阴影结构，由此在半导体本体之间限定有效区域。 所述方法还包括对所述栅极结构执行成角度的注入，其中所述阴影结构基本上阻止来自所述成角度植入物的掺杂物注入到所述有源区域中，以及对所述栅极结构和所述有源区域进行源极/漏极注入。

公开(公告)号：US20080268623A1

公开(公告)日：2008-10-30

申请号：US11739981

申请日：2007-04-25

申请人： Haowen Bu ,  Shashank S. Ekbote ,  Borna Obradovic ,  Srinivasan Chakravarthi

发明人： Haowen Bu ,  Shashank S. Ekbote ,  Borna Obradovic ,  Srinivasan Chakravarthi

IPC分类号： H01L21/425 ,  H01L21/26

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/324

摘要： A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal. The disclosure also pertains to semiconductor components produced in this manner, and various embodiments and improvements of such methods for producing such components.

摘要翻译： 公开了一种用于将诸如晶体管的源极或漏极区域的半导体衬底的目标区域掺杂到电子有源掺杂剂（例如用于在NMOS器件中产生有源区域的N型掺杂剂）或P 用于在PMOS器件中产生有源区）的具有良好控制的放置曲线和强激活。 该方法包括将目标区域中的含碳扩散抑制剂置于掺杂剂浓度的约50％处，并使掺杂剂活化约1,040摄氏度的热退火。 在许多情况下，在这样高的温度下的热退火引起掺杂剂离开目标区域的过度扩散，但这种相对浓度的碳在这样的高温热退火期间产生了掺杂剂扩散的意外的减少。 本公开还涉及以这种方式制造的半导体部件，以及用于制造这种部件的这种方法的各种实施例和改进。

公开(公告)号：US20110027954A1

公开(公告)日：2011-02-03

申请号：US12900821

申请日：2010-10-08

申请人： Borna Obradovic ,  Shashank S. Ekbote

发明人： Borna Obradovic ,  Shashank S. Ekbote

IPC分类号： H01L21/335 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/7848

摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.

摘要翻译： 提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。 门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。 在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。 半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。 通过选择性外延生长植入或生长源极/漏极区域。

公开(公告)号：US20090093095A1

公开(公告)日：2009-04-09

申请号：US11868787

申请日：2007-10-08

申请人： Borna Obradovic ,  Shashank S. Ekbote

发明人： Borna Obradovic ,  Shashank S. Ekbote

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/7848

摘要： A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.

摘要翻译： 提供一种形成晶体管器件的方法，其中栅极结构形成在第一导电类型的半导体本体上。 门结构被形成为包括其上的保护盖并且限定与其横向相邻的源/漏区。 在栅极结构和源极/漏极区域中进行第二导电类型的第一注入。 半导体本体被蚀刻以形成基本上对准栅极结构的凹槽，其中第一注入从源极/漏极区域移除。 通过选择性外延生长植入或生长源极/漏极区域。