公开(公告)号：US08785911B2

公开(公告)日：2014-07-22

申请号：US13167570

申请日：2011-06-23

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

IPC分类号： H01L21/336

CPC分类号： H01L29/7781 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/1075 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055

摘要： Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

摘要翻译： 提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。

公开(公告)号：US20120326126A1

公开(公告)日：2012-12-27

申请号：US13167570

申请日：2011-06-23

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han ,  James Bowler Hannon ,  Katherine L. Saenger ,  George Stojan Tulevski

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L29/7781 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/1075 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0023 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055

摘要： Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

摘要翻译： 提供具有基于纳米材料的通道（例如，碳纳米管或石墨烯通道）的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的局部底栅，其中栅极的顶表面与绝缘体的表面基本共面; 底栅上的局部栅极电介质; 在所述局部栅极电介质的至少一部分上的碳基纳米结构材料，其中所述碳基纳米结构材料的一部分用作所述器件的通道; 并且导电源极和漏极接触到用作器件的源极和漏极区域的沟道的相对侧上的碳基纳米结构材料的一个或多个部分。

公开(公告)号：US09076873B2

公开(公告)日：2015-07-07

申请号：US12986342

申请日：2011-01-07

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L29/49

CPC分类号： H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

公开(公告)号：US08890116B2

公开(公告)日：2014-11-18

申请号：US13610089

申请日：2012-09-11

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/06 ,  H01L51/00 ,  B82Y10/00 ,  H01L51/05

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

摘要翻译： 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US20120175594A1

公开(公告)日：2012-07-12

申请号：US12986342

申请日：2011-01-07

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/15 ,  H01L21/336

CPC分类号： H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

摘要翻译： 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

公开(公告)号：US20120032149A1

公开(公告)日：2012-02-09

申请号：US12850095

申请日：2010-08-04

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

摘要翻译： 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US09082856B2

公开(公告)日：2015-07-14

申请号：US13613198

申请日：2012-09-13

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L29/49

CPC分类号： H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

摘要翻译： 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

公开(公告)号：US20130015428A1

公开(公告)日：2013-01-17

申请号：US13610089

申请日：2012-09-11

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

摘要翻译： 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US08288759B2

公开(公告)日：2012-10-16

申请号：US12850095

申请日：2010-08-04

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/06

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

摘要翻译： 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US20130001519A1

公开(公告)日：2013-01-03

申请号：US13613198

申请日：2012-09-13

申请人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

发明人： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC分类号： H01L29/66

CPC分类号： H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.