公开(公告)号：US06985984B2

公开(公告)日：2006-01-10

申请号：US10289822

申请日：2002-11-07

申请人： Zoran Radovic ,  Erik Hagersten

发明人： Zoran Radovic ,  Erik Hagersten

IPC分类号： G06F12/14

CPC分类号： G06F9/52

摘要： A multiprocessing system including multiple processing nodes employs various implementations of hierarchical back-off locks. A thread attempting to obtain a software lock may determine whether the lock is currently owned by a different node than the node in which the thread is executing. If the lock is not owned by a different node, the thread executes code to perform a fast spin operation. On the other hand, if the lock is owned by a different node, the thread executes code to perform a slow spin operation. In this manner, node locality may result wherein a thread that is executing within the same node in which a lock has already been obtained will be more likely to subsequently acquire the lock when it is freed in relation to other contending threads executing in other nodes.

摘要翻译： 包括多个处理节点的多处理系统采用分级退回锁的各种实现。 尝试获取软件锁的线程可以确定该锁当前是否与线程正在执行的节点不同的节点拥有。 如果锁不是由不同节点拥有的，则线程执行代码以执行快速自旋操作。 另一方面，如果锁由不同的节点拥有，则线程执行代码以执行缓慢的旋转操作。 以这种方式，可能导致节点位置，其中在已经获得锁的同一节点内正在执行的线程相对于在其他节点中执行的其他竞争线程释放时，更可能随后获取锁定。

公开(公告)号：US20070255907A1

公开(公告)日：2007-11-01

申请号：US11413243

申请日：2006-04-28

申请人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

发明人： Hakan Zeffer ,  Erik Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul Loewenstein ,  Robert Cypher ,  Zoran Radovic

IPC分类号： G06F13/28

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US08732430B2

公开(公告)日：2014-05-20

申请号：US13069337

申请日：2011-03-22

申请人： Zoran Radovic ,  Graham Ricketson Murphy ,  Paul J. Jordan ,  John G. Johnson

发明人： Zoran Radovic ,  Graham Ricketson Murphy ,  Paul J. Jordan ,  John G. Johnson

IPC分类号： G06F12/10 ,  G06F12/02

CPC分类号： G06F12/10 ,  G06F8/315 ,  G06F12/02 ,  G06F12/0253

摘要： The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

摘要翻译： 所公开的实施例提供了使用存储器指针中的未使用位的系统。 在操作期间，系统确定地址空间中的一组地址位，在编程操作期间不需要寻址目的。 随后，系统将与存储器指针相关联的数据存储在该组地址位中。 当使用存储器指针访问与存储器指针相关联的存储器地址时，系统将对该组地址位进行掩蔽。 将附加数据存储在未使用的指针位中可以减少程序的存储器访问次数，并提高程序性能和/或可靠性。

公开(公告)号：US07080213B2

公开(公告)日：2006-07-18

申请号：US10320758

申请日：2002-12-16

申请人： Oskar Grenholm ,  Zoran Radovic ,  Erik E. Hagersten

发明人： Oskar Grenholm ,  Zoran Radovic ,  Erik E. Hagersten

IPC分类号： G06F12/00

CPC分类号： G06F12/0815

摘要： A system and method for reducing shared memory write overhead in multiprocessor system. In one embodiment, a multiprocessing system implements a method comprising storing an indication of obtained store permission corresponding to a particular address in a store buffer. The indication may be, for example, the address of a cache line for which a write permission has been obtained. Obtaining the write permission may include locking and modifying an MTAG or other coherence state entry. The method further comprises determining whether the indication of obtained store permission corresponds to an address of a write operation to be performed. In response to the indication corresponding to the address of the write operation to be performed, the write operation is performed without invoking corresponding global coherence operations.

摘要翻译： 一种用于在多处理器系统中减少共享内存写开销的系统和方法。 在一个实施例中，多处理系统实现一种方法，包括将对应于特定地址的获得的存储许可的指示存储在存储缓冲器中。 该指示可以是例如已获得写入许可的高速缓存线的地址。 获取写入许可可以包括锁定和修改MTAG或其他相干状态条目。 该方法还包括确定获得的存储许可的指示是否对应于要执行的写入操作的地址。 响应于与要执行的写入操作的地址对应的指示，执行写入操作而不调用相应的全局相干操作。

公开(公告)号：US08756363B2

公开(公告)日：2014-06-17

申请号：US13178240

申请日：2011-07-07

申请人： Zoran Radovic ,  Graham Ricketson Murphy ,  Bharat K. Daga

发明人： Zoran Radovic ,  Graham Ricketson Murphy ,  Bharat K. Daga

IPC分类号： G06F12/00

CPC分类号： G06F21/52 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1666

摘要： Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

摘要翻译： 处理器中有效的内存损坏检测的系统和方法。 处理器检测将在物理存储器中分配第一数据结构。 物理存储器可以是具有为硬件故障切换机制保留的备用存储体的DRAM。 处理器或操作系统（OS）都确定与第一数据结构对应的第一版本号。 在第一数据结构的初始化期间，第一版本号可以存储在备用存储体中的第一位置。 处理器从OS接收保持第一版本号的指针。 当处理器执行针对第一数据结构的存储器访问操作时，处理器将第一版本号与存储在由存储器访问地址指示的物理存储器中的位置中的第三版本号进行比较。 响应于确定不匹配，处理器可以设置陷阱。

公开(公告)号：US20110202725A1

公开(公告)日：2011-08-18

申请号：US12708376

申请日：2010-02-18

申请人： John R. Rose ,  Lawrence A. Spracklen ,  Zoran Radovic

发明人： John R. Rose ,  Lawrence A. Spracklen ,  Zoran Radovic

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F9/30021 ,  G06F9/30018

摘要： A method and processor supporting architected instructions for tracking and determining set membership, such as by implementing Bloom filters. The apparatus includes storage arrays (e.g., registers) and an execution core configured to store an indication that a given value is a member of a set, including by executing an architected instruction having an operand specifying the given value, wherein executing comprises hashing applying a hash function to the value to determine an index into one of the storage arrays and setting a bit of the storage array corresponding to the index. An architected query instruction is later executed to determine if a query value is not a member of the set, including by applying the hash function to the query value to determine an index into the storage array and determining whether a bit at the index of the storage array is set.

摘要翻译： 支持用于跟踪和确定集合成员资格的架构化指令的方法和处理器，例如通过实现Bloom过滤器。 该装置包括存储阵列（例如，寄存器）和被配置为存储给定值是组的成员的指示的执行核心，包括通过执行具有指定给定值的操作数的架构化指令，其中执行包括哈希应用 将hash函数的值确定为一个索引到一个存储阵列中，并设置一个与索引相对应的存储阵列。 稍后执行架构化查询指令以确定查询值是否不是该集合的成员，包括通过将哈希函数应用于查询值来确定存储阵列中的索引并确定存储器的索引处的位 数组被设置。

公开(公告)号：US20130036332A1

公开(公告)日：2013-02-07

申请号：US13198904

申请日：2011-08-05

申请人： Darryl J. Gove ,  Zoran Radovic ,  Jonathan Adams

发明人： Darryl J. Gove ,  Zoran Radovic ,  Jonathan Adams

IPC分类号： G06F11/14

CPC分类号： G06F21/52 ,  G06F11/0724 ,  G06F11/0763

摘要： Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

摘要翻译： 用于最大化用于内存损坏检测的版本号的可用状态数量的系统和方法。 物理存储器可以是包括多个区域的DRAM。 可以生成与物理存储器中分配的数据结构相关联的版本号，使得虚拟地址空间中的相邻数据结构的版本号不同。 保留集合和可用的版本号集合与多个区域中的每一个相关联。 给定区域的保留集合中的版本号可以在另一区域的可用集合中。 响应于至少确定存储在由存储器访问操作识别的第一区域中的存储器位置中的版本号也处于与第一区域相关联的保留集中，处理器不检测存储器损坏错误。

公开(公告)号：US20130013843A1

公开(公告)日：2013-01-10

申请号：US13178240

申请日：2011-07-07

申请人： Zoran Radovic ,  Graham Ricketson Murphy ,  Bharat K. Daga

发明人： Zoran Radovic ,  Graham Ricketson Murphy ,  Bharat K. Daga

IPC分类号： G06F12/06

CPC分类号： G06F21/52 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1666

摘要： Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

摘要翻译： 处理器中有效的内存损坏检测的系统和方法。 处理器检测将在物理存储器中分配第一数据结构。 物理存储器可以是具有为硬件故障切换机制保留的备用存储体的DRAM。 处理器或操作系统（OS）都确定与第一数据结构对应的第一版本号。 在第一数据结构的初始化期间，第一版本号可以存储在备用存储体中的第一位置。 处理器从OS接收保持第一版本号的指针。 当处理器执行针对第一数据结构的存储器访问操作时，处理器将第一版本号与存储在由存储器访问地址指示的物理存储器中的位置中的第三版本号进行比较。 响应于确定不匹配，处理器可以设置陷阱。

公开(公告)号：US07412567B2

公开(公告)日：2008-08-12

申请号：US11413243

申请日：2006-04-28

申请人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

发明人： Håkan E. Zeffer ,  Erik E. Hagersten ,  Anders Landin ,  Shailender Chaudhry ,  Paul N. Loewenstein ,  Robert E. Cypher ,  Zoran Radovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0808 ,  G06F12/0822 ,  G06F12/0897

摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

摘要翻译： 在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。 相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。 相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值匹配以相干地执行存储器操作。 陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。 在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

公开(公告)号：US08806145B2

公开(公告)日：2014-08-12

申请号：US12266719

申请日：2008-11-07

申请人： Zoran Radovic ,  Erik Martin Roland Karlsson

发明人： Zoran Radovic ,  Erik Martin Roland Karlsson

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.

摘要翻译： 公开了用于改善处理器中的投机成功的方法和装置。 在一些实施例中，该方法可以包括执行程序代码的多个线程，所述多个线程包括第一推测加载请求，响应于第一推测加载请求设置对应于高速缓存行的指示符位，并且在该事件中 来自多个线程的第二推测加载请求是指具有指示符位置位的第一高速缓存行，确定第二高速缓存行是否可用。