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公开(公告)号：US20230299759A1
公开(公告)日：2023-09-21
申请号：US17876503
申请日：2022-07-28
Applicant: Montage Electronics (Shanghai) Co., Ltd.
Inventor： Li Quan , Xuexin Ding , Liang Zhang , Zhongyuan Chang , Yufei Gu , Lixin Jiang , Gang Yan , Zongjie Hu
IPC: H03K5/1534 , H03K5/1252
CPC classification number: H03K5/1534 , H03K5/1252
Abstract: The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.
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公开(公告)号：US20240429903A1
公开(公告)日：2024-12-26
申请号：US18648472
申请日：2024-04-28
Applicant: Montage Electronics (Shanghai) Co., Ltd.
Inventor： Juan DU , Chunlai SUN , Yuchen TIAN
IPC: H03K3/037 , H03K3/012 , H03K3/356 , H03K19/0185
Abstract: An output driving circuit, a clock chip, and an electronic device are provided. The output driving circuit includes a low-voltage push-pull module and an output isolation module, wherein the low-voltage push-pull module is connected to a low-voltage bias voltage and is configured to receive and process a high-speed input signal, and to output an intermediate signal having a target level, wherein the low-voltage push-pull module includes one or more push-pull units, each including a low-voltage transistor pair, wherein the output isolation module is connected between an output terminal of the low-voltage push-pull module and an output terminal of the output driving circuit, wherein the output isolation module is configured to be turned on when the output driving circuit works normally, and to output the intermediate signal as a target output signal of the output driving circuit. The output driving circuit has lower power consumption.
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公开(公告)号：US12080369B2
公开(公告)日：2024-09-03
申请号：US17577400
申请日：2022-01-18
Applicant: MONTAGE ELECTRONICS (SHANGHAI) CO., LTD.
Inventor： Christopher Cox , Leechung Yiu , Robert Xi Jin , Zheng Qiu , Leonard Datus , Lizhi Jin
CPC classification number: G11C5/04 , H05K1/181 , H05K5/0286
Abstract: A memory device with modular design and the memory system comprising the same is disclosed. The memory device comprises a substrate plate having a front edge, a rear edge opposite to the front edge, and a top side and a bottom side which are opposite to each other and extend between the front edge and the rear edge; an edge connector positioned at the rear edge and configured to connect to a host connector of a host device; a memory control module positioned on one of the top side and the bottom side of the substrate plate; at least one socket positioned on the top side of the substrate plate and configured to connect to at least one removable memory module; and wherein the memory controller module is electrically coupled to the edge connector and the at least one socket such that the at least one memory module can be accessible by the host device via the memory control module.
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公开(公告)号：US20230215474A1
公开(公告)日：2023-07-06
申请号：US17577400
申请日：2022-01-18
Applicant: MONTAGE ELECTRONICS (SHANGHAI) CO., LTD.
Inventor： Christopher COX , Leechung YIU , Robert Xi JIN , Zheng QIU , Leonard DATUS , Lizhi JIN
CPC classification number: G11C5/04 , H05K5/0286 , H05K1/181
Abstract: A memory device with modular design and the memory system comprising the same is disclosed. The memory device comprises a substrate plate having a front edge, a rear edge opposite to the front edge, and a top side and a bottom side which are opposite to each other and extend between the front edge and the rear edge; an edge connector positioned at the rear edge and configured to connect to a host connector of a host device; a memory control module positioned on one of the top side and the bottom side of the substrate plate; at least one socket positioned on the top side of the substrate plate and configured to connect to at least one removable memory module; and wherein the memory controller module is electrically coupled to the edge connector and the at least one socket such that the at least one memory module can be accessible by the host device via the memory control module.
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公开(公告)号：US20220334993A1
公开(公告)日：2022-10-20
申请号：US17564146
申请日：2021-12-28
Applicant: Montage Electronics (Shanghai) Co., Ltd.
Inventor： Shuyong DENG , Zeqiang FU , Hankang LI , Yuxiang LIAO , Xin LIU , Yu FU
Abstract: The present disclosure provides a hot-plugging control method, device, and retimer. The hot-plugging control method includes: receiving data from a pluggable device through a second end, sending the data to an RC through a first end; sending a detection signal to the second end to detect the connection status between the pluggable device and the second end; and stopping sending the data to the RC, and sending the first control signal to the RC, when it is detected that the pluggable device is hot-unplugged from the second end, so that the RC handles the abnormal state of the data not being sent according to the first control signal. The hot-plugging control method provided by the present disclosure does not require presence signals to implement hot-plugging of a pluggable device, and thus can avoid the problem that the device cannot implement hot-plugging without presence signals.
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Patent Agency Ranking
公开(公告)号：US20250047287A1
公开(公告)日：2025-02-06
申请号：US18792540
申请日：2024-08-01
Applicant: Montage Electronics (Shanghai) Co., Ltd.
Inventor： Qiuyan Zu , Gang Yan , Yong Wang , Pengzhan Zhang
Abstract: The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.
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公开(公告)号：US20240378057A1
公开(公告)日：2024-11-14
申请号：US18633517
申请日：2024-04-12
Applicant: Montage Electronics (Shanghai) Co., Ltd.
IPC: G06F9/30
Abstract: A data padding method comprises: determining a length of a space occupied by remaining data in the register; comparing the length of the space occupied; performing, when the length of the space occupied by the remaining data is less than the length of the unit input data, following operations: receiving a unit input data and storing it continuously with the remaining data in the register; determining a length of a unit output data to be output; intercepting a portion of data with a length of N words from data formed by padding the remaining data buffered in the register and the unit input data and starting from an address space of a lowest bit of the register, as the unit output data and outputting it; and shifting the data remaining in the register as a whole to an address space in the register starting from the lowest bit.
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公开(公告)号：US20240364319A1
公开(公告)日：2024-10-31
申请号：US18636983
申请日：2024-04-16
Applicant: MONTAGE ELECTRONICS (SHANGHAI) CO., LTD.
Inventor： Pingshun MA , Bo QU
CPC classification number: H03K5/13 , H03K3/037 , H03K2005/00052
Abstract: The application relates to the field of integrated circuit design and discloses a digital phase interpolator, comprising: a first delay unit, a pre-interpolating unit, a second delay unit, and a phase interpolating unit; wherein each interpolation branch comprises a pre-interpolating unit and a re-interpolating unit. For two input signals with preset phase differences, the digital phase interpolator performs two interpolation processes, one at the pre-interpolating unit and the other at the phase interpolating unit. This distributed quadratic interpolation reduces the task of the phase interpolation unit, helps to reduce the number of stages of the phase interpolating unit, reduces the input load, reduces the overall power consumption and the overall area, ensures the rationality of its own power consumption, and improves the linearity of phase interpolation to some extent.
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公开(公告)号：US11888970B2
公开(公告)日：2024-01-30
申请号：US17505023
申请日：2021-10-19
Applicant: MONTAGE ELECTRONICS (SHANGHAI) CO., LTD.
Inventor： Zhaohui Du
CPC classification number: H04L9/0825 , G06F17/16 , H04L9/0866 , H04L9/3239
Abstract: The present disclosure provides systems and methods for deriving a key from a basekey built-in a chip is provided. In an exemplary embodiment, there is provided a method for deriving a key from basekey built-in a chip that may comprise obtaining a basekey built-in the chip and a current version number when the chip starts up and runs read-only boot code, and performing iterations on the basekey via a one-way function to obtain a derived key of the current version. The number of times of the iterations is equal to the difference between a maximum version number and the current version number.
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公开(公告)号：US11750184B1
公开(公告)日：2023-09-05
申请号：US17876503
申请日：2022-07-28
Applicant: Montage Electronics (Shanghai) Co., Ltd.
Inventor： Li Quan , Xuexin Ding , Liang Zhang , Zhongyuan Chang , Yufei Gu , Lixin Jiang , Gang Yan , Zongjie Hu
IPC: H03K5/00 , H03K5/1534 , H03K5/1252 , H03K5/01
CPC classification number: H03K5/1534 , H03K5/1252 , H03K5/01
Abstract: The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.
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