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公开(公告)号：US12080369B2
公开(公告)日：2024-09-03
申请号：US17577400
申请日：2022-01-18
发明人： Christopher Cox , Leechung Yiu , Robert Xi Jin , Zheng Qiu , Leonard Datus , Lizhi Jin
CPC分类号： G11C5/04 , H05K1/181 , H05K5/0286
摘要： A memory device with modular design and the memory system comprising the same is disclosed. The memory device comprises a substrate plate having a front edge, a rear edge opposite to the front edge, and a top side and a bottom side which are opposite to each other and extend between the front edge and the rear edge; an edge connector positioned at the rear edge and configured to connect to a host connector of a host device; a memory control module positioned on one of the top side and the bottom side of the substrate plate; at least one socket positioned on the top side of the substrate plate and configured to connect to at least one removable memory module; and wherein the memory controller module is electrically coupled to the edge connector and the at least one socket such that the at least one memory module can be accessible by the host device via the memory control module.
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公开(公告)号：US20230215474A1
公开(公告)日：2023-07-06
申请号：US17577400
申请日：2022-01-18
发明人： Christopher COX , Leechung YIU , Robert Xi JIN , Zheng QIU , Leonard DATUS , Lizhi JIN
CPC分类号： G11C5/04 , H05K5/0286 , H05K1/181
摘要： A memory device with modular design and the memory system comprising the same is disclosed. The memory device comprises a substrate plate having a front edge, a rear edge opposite to the front edge, and a top side and a bottom side which are opposite to each other and extend between the front edge and the rear edge; an edge connector positioned at the rear edge and configured to connect to a host connector of a host device; a memory control module positioned on one of the top side and the bottom side of the substrate plate; at least one socket positioned on the top side of the substrate plate and configured to connect to at least one removable memory module; and wherein the memory controller module is electrically coupled to the edge connector and the at least one socket such that the at least one memory module can be accessible by the host device via the memory control module.
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公开(公告)号：US20220334993A1
公开(公告)日：2022-10-20
申请号：US17564146
申请日：2021-12-28
发明人： Shuyong DENG , Zeqiang FU , Hankang LI , Yuxiang LIAO , Xin LIU , Yu FU
摘要： The present disclosure provides a hot-plugging control method, device, and retimer. The hot-plugging control method includes: receiving data from a pluggable device through a second end, sending the data to an RC through a first end; sending a detection signal to the second end to detect the connection status between the pluggable device and the second end; and stopping sending the data to the RC, and sending the first control signal to the RC, when it is detected that the pluggable device is hot-unplugged from the second end, so that the RC handles the abnormal state of the data not being sent according to the first control signal. The hot-plugging control method provided by the present disclosure does not require presence signals to implement hot-plugging of a pluggable device, and thus can avoid the problem that the device cannot implement hot-plugging without presence signals.
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公开(公告)号：US20230299759A1
公开(公告)日：2023-09-21
申请号：US17876503
申请日：2022-07-28
发明人： Li Quan , Xuexin Ding , Liang Zhang , Zhongyuan Chang , Yufei Gu , Lixin Jiang , Gang Yan , Zongjie Hu
IPC分类号： H03K5/1534 , H03K5/1252
CPC分类号： H03K5/1534 , H03K5/1252
摘要： The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.
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公开(公告)号：US20240364319A1
公开(公告)日：2024-10-31
申请号：US18636983
申请日：2024-04-16
发明人： Pingshun MA , Bo QU
CPC分类号： H03K5/13 , H03K3/037 , H03K2005/00052
摘要： The application relates to the field of integrated circuit design and discloses a digital phase interpolator, comprising: a first delay unit, a pre-interpolating unit, a second delay unit, and a phase interpolating unit; wherein each interpolation branch comprises a pre-interpolating unit and a re-interpolating unit. For two input signals with preset phase differences, the digital phase interpolator performs two interpolation processes, one at the pre-interpolating unit and the other at the phase interpolating unit. This distributed quadratic interpolation reduces the task of the phase interpolation unit, helps to reduce the number of stages of the phase interpolating unit, reduces the input load, reduces the overall power consumption and the overall area, ensures the rationality of its own power consumption, and improves the linearity of phase interpolation to some extent.
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公开(公告)号：US11888970B2
公开(公告)日：2024-01-30
申请号：US17505023
申请日：2021-10-19
发明人： Zhaohui Du
CPC分类号： H04L9/0825 , G06F17/16 , H04L9/0866 , H04L9/3239
摘要： The present disclosure provides systems and methods for deriving a key from a basekey built-in a chip is provided. In an exemplary embodiment, there is provided a method for deriving a key from basekey built-in a chip that may comprise obtaining a basekey built-in the chip and a current version number when the chip starts up and runs read-only boot code, and performing iterations on the basekey via a one-way function to obtain a derived key of the current version. The number of times of the iterations is equal to the difference between a maximum version number and the current version number.
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公开(公告)号：US11750184B1
公开(公告)日：2023-09-05
申请号：US17876503
申请日：2022-07-28
发明人： Li Quan , Xuexin Ding , Liang Zhang , Zhongyuan Chang , Yufei Gu , Lixin Jiang , Gang Yan , Zongjie Hu
IPC分类号： H03K5/00 , H03K5/1534 , H03K5/1252 , H03K5/01
CPC分类号： H03K5/1534 , H03K5/1252 , H03K5/01
摘要： The disclosure provides a glitch removal circuit with low latency. The glitch removal circuit includes a first signal edge detector, a second signal edge detector, a latch, and a control signal generator. The first signal edge detector is activated according to the first control signal to detect the rising edge of the input signal to generate the first detection result. The second signal edge detector is activated according to the second control signal to detect the falling edge of the input signal to generate the second detection result. The latch sets the generated output signal according to the first detection result, and clears the generated output signal according to the second detection result. The control signal generator shields the glitch on the input signal to generate a processed signal, and generates a first control signal and a second control signal according to the processed signal.
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公开(公告)号：US11748286B2
公开(公告)日：2023-09-05
申请号：US17564146
申请日：2021-12-28
发明人： Shuyong Deng , Zeqiang Fu , Hankang Li , Yuxiang Liao , Xin Liu , Yu Fu
CPC分类号： G06F13/4004 , G06F13/4221 , G06F2213/0026 , G06F2213/40
摘要： The present disclosure provides a hot-plugging control method, device, and retimer. The hot-plugging control method includes: receiving data from a pluggable device through a second end, sending the data to an RC through a first end; sending a detection signal to the second end to detect the connection status between the pluggable device and the second end; and stopping sending the data to the RC, and sending the first control signal to the RC, when it is detected that the pluggable device is hot-unplugged from the second end, so that the RC handles the abnormal state of the data not being sent according to the first control signal. The hot-plugging control method provided by the present disclosure does not require presence signals to implement hot-plugging of a pluggable device, and thus can avoid the problem that the device cannot implement hot-plugging without presence signals.
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公开(公告)号：US20230214178A1
公开(公告)日：2023-07-06
申请号：US18146992
申请日：2022-12-27
发明人： Zhijie LIU , Jinfeng JI , Jie DAI
IPC分类号： G06F7/16 , G06F16/901 , G06F16/23
CPC分类号： G06F7/16 , G06F16/901 , G06F16/2365
摘要： The present application relates to a device for selecting top values from a set of raw values, comprising: an output queue, a loop queue, a top value storage module and a control module. The control module is configured to, at a higher priority, merge the intermediate sequence stored in the loop queue with the at most N top values stored in a storage area of the top value storage module, and sort the merged values to generate a merged sequence, until a predetermined number of storage areas in the top value storage module are traversed; wherein the control module is further configured to, when there is no intermediate sequence being stored in the loop queue, merge the output sequence with the at most N top values stored in a storage area of the top value storage module, and sort the merged values to generate a merged sequence; wherein the control module is further configured to provide a first subsequence in the merged sequence which is closer to a top most value of the merged sequence to the top value storage module to update the top value storage module, and provide a second subsequence in the merged sequence which is farther away from the top most value of the merged sequence to the loop queue to generate or update the intermediate sequence.
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公开(公告)号：US12127361B2
公开(公告)日：2024-10-22
申请号：US17577393
申请日：2022-01-18
发明人： Christopher Cox , Leechung Yiu , Robert Xi Jin , Zheng Qiu , Leonard Datus , Lizhi Jin
CPC分类号： H05K5/026 , G11C5/04 , H05K5/0026 , H05K7/1427 , H05K7/20445
摘要： The present application provides a memory device. The memory device includes a connector plate having a front edge and a rear edge opposite to the front edge, wherein the connector plate comprises an edge connector disposed at the rear edge and configured to connect to a host connector of a host device; a controller plate defining a first connection region, a second connection region and a chip region, wherein the controller plate is attached to the connector plate at the first connection region, and the controller plate comprises a memory control module disposed in the chip region and in electrical communication with the edge connector; and at least one memory module detachably connected to the controller plate at the second connection region of the controller plate, wherein each of the at least one memory module is in electrical communication with the memory control module when the memory module is connected to the controller plate, such that the memory module can be accessible by the host device via the memory control module.
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