公开(公告)号：US20030231540A1

公开(公告)日：2003-12-18

申请号：US10174867

申请日：2002-06-18

申请人： Nanoamp Solutions, Inc. ,  Nanoamp Solutions, Inc.

发明人： Paul S. Lazar ,  Seung Cheol Oh

IPC分类号： G11C007/00

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615

摘要： Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.

摘要翻译： 内部刷新一个或多个DRAM阵列，而不需要额外的外部命令信号。 刷新周期和/或读/写访问周期的调度使用仲裁和选择电路，其接收来自独立振荡器的刷新请求输入信号和行访问选择RAS输入信号。 字线地址复用器将内部提供的刷新或外部提供的行行地址信号提供给字线解码器。 刷新行计数器使用令牌状态信号一次仅激活一个刷新行计数器。 通过控制每个DRAM块中的单元数量来控制瞬时刷新功率。 仲裁和控制系统包括具有用于解决亚稳态的延迟的地址转换块，刷新控制块，RAS控制块和临时存储未选择的请求的仲裁电路。

公开(公告)号：US20090085671A1

公开(公告)日：2009-04-02

申请号：US12236344

申请日：2008-09-23

申请人： David H. Shen ,  James Burnham ,  Ali Tabatabaei ,  Ann P. Shen

发明人： David H. Shen ,  James Burnham ,  Ali Tabatabaei ,  Ann P. Shen

IPC分类号： H03F3/68 ,  H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03F2203/45638 ,  H03F2203/7209

摘要： Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

摘要翻译： 共享一个或多个负载电感器包括在第一放大器的第一端接收第一输入信号，并使用第一放大器放大第一输入信号。 第一放大器耦合到第一放大器的第二端处的一个或多个负载电感器，并且耦合到第一放大器的第三端处的一个或多个专用源电感器。 此外，在第二放大器的第一端处接收第二输入信号，该第二放大器使用第二放大器放大第二输入信号。 第二放大器耦合到第二放大器的第二端处的一个或多个负载电感器，并且耦合到第二放大器的第三端处的一个或多个专用源电感器。

公开(公告)号：US20090085545A1

公开(公告)日：2009-04-02

申请号：US12175316

申请日：2008-07-17

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： G05F1/565

CPC分类号： G05F1/565

摘要： In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode.

摘要翻译： 在一些实施方式中，系统包括能够在三种功率模式之间切换的低功率稳压器：电源关闭模式，低功率模式和较高功率模式。 该系统包括耦合到电压调节器以在低功率模式和较高功率模式之间切换的选择器，以及在功率关断模式和低功率或更高功率模式之间切换的开关。 该系统还具有控制电路，用于控制开关和选择器，以控制三种功率模式中的任何一种电压调节器的工作。 在低功率模式下，电压调节器中使用的总电流为微安或纳秒级。 低功耗模式下的电压调节器在较高功率模式下具有比电压调节器低两到几个数量级的低电流使用。

公开(公告)号：US20080102778A1

公开(公告)日：2008-05-01

申请号：US11764095

申请日：2007-06-15

申请人： David H. Shen

发明人： David H. Shen

IPC分类号： H04B1/28

CPC分类号： H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/1475 ,  H03D7/165

摘要： Particular embodiments of mixer designs permit greater integration on standard chips with an improvement in power and linearity to enable low-power, high-performance reception. Some embodiments feature a method of frequency conversion using at least two stages of switches to mix an input signal with reference signals. The method involves mixing a differential input signal with a first differential reference signal through a first stage of switches, generating from the first stage of switches a first frequency converted differential signal, and mixing the first frequency converted differential signal with a second differential reference signal through a second stage of switches. The method includes generating from the second stage of switches a second frequency converted differential signal. The first differential reference signal can be phase shifted from the second differential reference signal and can have a different frequency. The mixer designs can have multiple stages of switches in a low-supply voltage design.

摘要翻译： 混频器设计的特定实施例允许在标准芯片上进行更大的集成，具有功率和线性度的改善以实现低功率，高性能的接收。 一些实施例的特征在于使用至少两级开关的频率转换方法来将输入信号与参考信号混合。 该方法包括通过第一级开关将差分输入信号与第一差分参考信号混合，从开关的第一级产生第一变频差分信号，并将第一频率转换的差分信号与第二差分参考信号通过 第二级开关。 该方法包括从第二级切换产生第二频率转换的差分信号。 第一差分参考信号可以从第二差分参考信号相移并且可以具有不同的频率。 混频器设计可以在低电压电压设计中具有多级开关。

公开(公告)号：US07299020B2

公开(公告)日：2007-11-20

申请号：US10729674

申请日：2003-12-05

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： H04B1/18

CPC分类号： H04B1/005 ,  H04B1/28 ,  H04B1/30 ,  H04B1/406

摘要： A multiple frequency RF communications receiver is disclosed which permits greater integration on standard silicon chips and consumes less power than previous receivers. A new method for selecting the various frequency bands with a high amount of isolation and low power consumption is described. Compared to previous receiver implementations, there is no loss of selectivity in the receiver.

摘要翻译： 公开了一种多频RF通信接收机，其允许在标准硅芯片上的更大集成并且消耗比先前的接收机更少的功率。 描述了一种用于选择具有大量隔离和低功耗的各种频带的新方法。 与以前的接收机实现相比，接收机中没有选择性的损失。

公开(公告)号：US5963071A

公开(公告)日：1999-10-05

申请号：US10805

申请日：1998-01-22

申请人： Ahmad Dowlatabadi

发明人： Ahmad Dowlatabadi

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03K5/156 ,  H03K3/017

CPC分类号： H03K5/00006 ,  H03K5/13 ,  H03K5/1565

摘要： An adjustable duty-cycle circuit includes an EXCLUSIVE-OR circuit for combining a divided reference input signal at a frequency .function..sub.IN /2 with a variably delayed divided reference input signal to provide an output frequency V.sub.O at .function..sub.IN with an adjustable duty cycle. A variable delay circuit, or delay line, is controlled by a control signal which is generated by comparing a signal equal to the average (DC) value of V.sub.O with an adjustable DC reference signal from a voltage divider or a DAC. An output signal from the comparator is filtered to provide the control signal V.sub.C for the delay circuit to control the duty cycle of the output signal. To provide a frequency doubler, the reference input signal is not divided by two to thereby obtain an output signal at 2.function..sub.IN with an adjustable duty cycle. Frequency multipliers for N=3, 5, 7, etc. are implemented with additional delays and exclusive logic circuits.

摘要翻译： 一个可调占空比电路包括一个独占电路，用于将频率为fIN / 2的分频参考输入信号与可变延迟的分频参考输入信号相组合，以提供具有可调占空比的fIN输出频率VO。 可变延迟电路或延迟线由控制信号控制，该控制信号通过将等于VO的平均值（DC）的信号与来自分压器或DAC的可调直流参考信号进行比较而产生。 来自比较器的输出信号被滤波以提供延迟电路的控制信号VC来控制输出信号的占空比。 为了提供倍频器，参考输入信号不被二分频，从而以可调占空比在2fIN处获得输出信号。 用于N = 3,5,7等的频率乘法器具有附加的延迟和专用逻辑电路。

公开(公告)号：US07521976B1

公开(公告)日：2009-04-21

申请号：US11296549

申请日：2005-12-07

申请人： Douglas Sudjian ,  David H. Shen

发明人： Douglas Sudjian ,  David H. Shen

IPC分类号： H03K3/00

CPC分类号： H03K3/356139 ,  H03K3/012

摘要： A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

摘要翻译： 公开了可以在高速输入时钟频率下工作的高速锁存器。 在闩锁设计中使用的有源负载表现出对电路的其余部分感应的输入阻抗，以在存在负载电容的情况下改善整个锁存器的驱动能力。 锁存电路在系统或独立分压器中使用时，将消耗非常低的功率，同时减少硅芯片面积。 可能的应用包括但不限于分频和计数应用。 特别感兴趣的是在预分频器分频器中使用该高速锁存器作为用于单芯片CMOS多频和多标准射频收发器集成电路的电荷泵锁相环设计的一部分。

公开(公告)号：US20090086806A1

公开(公告)日：2009-04-02

申请号：US12199092

申请日：2008-08-27

申请人： Chien-Meen Hwang ,  Ann P. Shen

发明人： Chien-Meen Hwang ,  Ann P. Shen

IPC分类号： H04L27/01

CPC分类号： H04L25/03006 ,  H04L2025/03535 ,  H04L2025/03745

摘要： In some implementations, a signal is received at a device and a gain change is detected in a component of the device that affects the signal. A state of an equalizer is adjusted in response to the detected gain change to a first state that reduces transient effects introduced into the signal by one or more components in the device as a result of the gain change. The signal is equalized using the equalizer with the state set to the first state and the state of the equalizer is adjusted from the first state to a second state while equalizing the signal using the equalizer such that the second state passes the signal through the equalizer substantially unchanged.

摘要翻译： 在一些实现中，在设备处接收信号，并且在影响信号的设备的部件中检测到增益改变。 调整均衡器的状态以响应于检测到的增益改变为第一状态，其通过增益改变的结果减少由设备中的一个或多个组件引入到信号中的瞬态效应。 使用均衡器将信号均衡，将均衡器的状态设置为第一状态，并且均衡器的状态从第一状态调整到第二状态，同时使用均衡器对信号进行均衡，使得第二状态基本上通过均衡器 不变

公开(公告)号：US20090085622A1

公开(公告)日：2009-04-02

申请号：US12110048

申请日：2008-04-25

申请人： David H. Shen ,  Ann P. Shen ,  Axel Schuur

发明人： David H. Shen ,  Ann P. Shen ,  Axel Schuur

IPC分类号： H03L7/06

CPC分类号： H03L7/183 ,  H03L7/10

摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

摘要翻译： 实现功能用于锁相环（PLL）的系统和技术。 在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作 在PLL操作启动期间振荡器。 在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。

公开(公告)号：US20090079497A1

公开(公告)日：2009-03-26

申请号：US12114344

申请日：2008-05-02

申请人： Axel Schuur ,  Ann Shen

发明人： Axel Schuur ,  Ann Shen

IPC分类号： H03B19/12 ,  H03D3/22

CPC分类号： H03D3/009 ,  H03D7/18

摘要： A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.

摘要翻译： 差分分频器包括每个被配置为接收差分输入信号的第一和第二输入端。 分频器还包括被配置为产生第一输出信号的第一输出端和被配置为产生第二输出信号的第二输出端。 分压器还包括耦合到第一输出端的第三输入端和耦合到第二输出端的第四输入端。 此外，分频器包括第一可变电流源。 改变第一可变电流源的电流导致第一输出端的第一输出信号和第二输出端的第二输出信号之间的相位差的改变。