公开(公告)号：US07521976B1

公开(公告)日：2009-04-21

申请号：US11296549

申请日：2005-12-07

申请人： Douglas Sudjian ,  David H. Shen

发明人： Douglas Sudjian ,  David H. Shen

IPC分类号： H03K3/00

CPC分类号： H03K3/356139 ,  H03K3/012

摘要： A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

摘要翻译： 公开了可以在高速输入时钟频率下工作的高速锁存器。 在闩锁设计中使用的有源负载表现出对电路的其余部分感应的输入阻抗，以在存在负载电容的情况下改善整个锁存器的驱动能力。 锁存电路在系统或独立分压器中使用时，将消耗非常低的功率，同时减少硅芯片面积。 可能的应用包括但不限于分频和计数应用。 特别感兴趣的是在预分频器分频器中使用该高速锁存器作为用于单芯片CMOS多频和多标准射频收发器集成电路的电荷泵锁相环设计的一部分。

公开(公告)号：US20080191783A1

公开(公告)日：2008-08-14

申请号：US11351696

申请日：2006-02-10

申请人： Douglas Sudjian ,  David H. Shen

发明人： Douglas Sudjian ,  David H. Shen

IPC分类号： G05F1/10

CPC分类号： H03L7/0896 ,  H03L7/0895

摘要： A charge pump replica bias detector is disclosed which provides a charge pump with a greater working output voltage range or larger output compliance. A larger working range will provide a charge pump with more symmetric source and sink currents than prior designs with a reduction of the multiple frequency sideband levels that occur in a voltage controlled oscillator of a phase-locked loop synthesizer. Further improvements are the prevention of disturbances of the loop filter voltage level due to unwanted leakage currents in a charge pump that are dependent on the value of loop filter voltage. Finally, by providing improved output voltage compliance and limiting loop filter voltage disturbances there are improvements in the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked loop designs for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

摘要翻译： 公开了一种电荷泵复制偏压检测器，其为电荷泵提供更大的工作输出电压范围或更大的输出顺应性。 较大的工作范围将为电荷泵提供比现有设计更为对称的源极和吸收电流，同时降低在锁相环合成器的压控振荡器中发生的多频边带电平。 进一步的改进是防止由于电荷泵中不必要的泄漏电流而导致的环路滤波器电压电平的干扰，这取决于环路滤波器电压的值。 最后，通过提供改进的输出电压一致性和限制环路滤波器电压扰动，在锁相环中参考频率馈通，电荷共享和噪声瞬态耦合以及相位噪声的降低有所改进。 可能的应用包括但不限于单芯片CMOS多频和多标准射频收发器集成电路的电荷泵锁相环设计。

公开(公告)号：US07015736B1

公开(公告)日：2006-03-21

申请号：US10890033

申请日：2004-07-13

申请人： Douglas Sudjian ,  David H. Shen

发明人： Douglas Sudjian ,  David H. Shen

IPC分类号： H03L7/06

CPC分类号： H03L7/0896 ,  H03L7/0895

摘要： A charge pump is disclosed which generates higher and more symmetric source and sink currents that prior designs and reduces the multiple frequency sidebands that occur in a voltage controlled oscillator of a phase-loop synthesizer. Other improvements are the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked designs for single chip CMOS multi-band and multi-standard radio frequency integrated circuits.

摘要翻译： 公开了一种电荷泵，其产生更高和更对称的源极和吸收电流，其先前设计和减少在相位合成器的压控振荡器中发生的多个频带边带。 其他改进是在锁相环中减少参考频率馈通，电荷共享和噪声瞬态耦合以及相位噪声。 可能的应用包括但不限于用于单芯片CMOS多频和多标准射频集成电路的电荷泵锁相设计。

公开(公告)号：US20100329157A1

公开(公告)日：2010-12-30

申请号：US12495064

申请日：2009-06-30

申请人： Nianwei Xing ,  David H. Shen ,  Axel Schuur ,  Ann P. Shen

发明人： Nianwei Xing ,  David H. Shen ,  Axel Schuur ,  Ann P. Shen

IPC分类号： H04B7/005 ,  H03F3/45 ,  G06G7/12

CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F2203/45342

摘要： Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.

摘要翻译： 用于差分电路的电路和方法涉及具有多对具有背栅极端子的差分晶体管中的一个，其中每个背栅极端子被可调谐的栅极电压偏置以补偿差分电路中的电路不匹配并且减小 或消除输出信号中的偶次谐波。 补偿电路可以被配置为接收与差分电路的差分输出信号相关的数据，并且向差分晶体管的背栅极端子提供一个或多个反向栅极电压，以调整差分晶体管的阈值电压并抑制 差分电路的差分输出信号中的偶次谐波。

公开(公告)号：US07646325B2

公开(公告)日：2010-01-12

申请号：US12187632

申请日：2008-08-07

申请人： Axel Schuur ,  David H. Shen ,  Ann P. Shen

发明人： Axel Schuur ,  David H. Shen ,  Ann P. Shen

IPC分类号： H03M1/12

CPC分类号： H03M3/374 ,  H03M3/43 ,  H03M3/438

摘要： An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

摘要翻译： 诸如CT SD-ADC的ADC包括产生充电和放电时钟信号的时钟产生电路，使得ADC中积分器的稳定时间增加。 时钟信号可以控制CT SD-ADC中的反馈SD-DAC。 时钟信号也可以是不对称的和/或可以导致积分器的建立时间大于系统时钟的一半。

公开(公告)号：US07532079B2

公开(公告)日：2009-05-12

申请号：US11764701

申请日：2007-06-18

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： H03B5/00

CPC分类号： H03B5/366 ,  H03B2201/0208 ,  H03J2200/10

摘要： Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

摘要翻译： 实施例用于数字调谐晶体振荡器电路的技术和系统。 在一个方面，实施例的特征在于制造数字调谐晶体振荡器电路的方法。 该方法包括将多位输入信号接收到数字调制器中，通过过采样或通过噪声整形和过采样来调制具有数字调制器的多位输入信号，以产生具有比多数位更低位数的数字调制输出信号 位输入信号。 该方法还涉及将调谐电容器与晶体振荡器电路耦合，并将数字调制输出信号从数字调制器耦合到晶体振荡器电路和调谐电容器。 在一些实施例中，数字调制器可以是Δ-Σ调制器，噪声调制器，Δ调制器，脉冲宽度调制器，差分调制器或连续斜率增量调制器。

公开(公告)号：US20090088091A1

公开(公告)日：2009-04-02

申请号：US12240498

申请日：2008-09-29

申请人： David H. Shen ,  Chien-Meen Hwang ,  Ann P. Shen

发明人： David H. Shen ,  Chien-Meen Hwang ,  Ann P. Shen

IPC分类号： H04B1/02

CPC分类号： H04B1/0483 ,  H04B2001/0491

摘要： Generally, implementations provide a circuit framework that uses phase and amplitude modulation with several voltage-controlled-oscillators (VCOs) and corresponding variable gain amplifiers (VGAs) to generate and amplitude and phase modulated signals that are summed to an output signal for a transmitter circuit. The implementations can involve decomposing an input signal into a number of decomposed signals using a signal decomposer component, in which each of decomposed signals includes phase and amplitude information. The signal decomposer component can interact with each of the VCOs and corresponding VGAs to conduct the phase and amplitude modulation for the amplitude and phase modulated signals. The multiple standard transmitter circuit can be used for one or more communication standards, such as Global System for Mobile Communications (GSM), a Wideband Code Division Multiple Access (WCDMA), or High-Speed Uplink Packet Access (HSUPA), among others.

摘要翻译： 通常，实施方案提供了一种电路框架，其使用相位和幅度调制与若干电压控制振荡器（VCO）和相应的可变增益放大器（VGA）产生并将幅度和相位调制信号相加到发射机电路的输出信号 。 这些实现可以包括使用信号分解器组件将输入信号分解成多个分解信号，其中每个分解信号包括相位和幅度信息。 信号分解器组件可以与每个VCO和对应的VGA相互作用，以对振幅和相位调制信号进行相位和幅度调制。 多标准发射机电路可以用于诸如全球移动通信系统（GSM），宽带码分多址（WCDMA）或高速上行链路分组接入（HSUPA）等一种或多种通信标准。

公开(公告)号：US07248850B2

公开(公告)日：2007-07-24

申请号：US10729638

申请日：2003-12-05

申请人： David H. Shen

发明人： David H. Shen

IPC分类号： H04B1/28

CPC分类号： H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/1475 ,  H03D7/165

摘要： A mixer design is described that permits greater integration on standard silicon chips with an improvement in power and linearity compared to previous mixer designs, enabling low-power, high performance RF reception.

摘要翻译： 描述了一种混频器设计，与以前的混频器设计相比，允许在标准硅芯片上更大程度地集成功率和线性度，从而实现低功率，高性能RF接收。

公开(公告)号：US20090085671A1

公开(公告)日：2009-04-02

申请号：US12236344

申请日：2008-09-23

申请人： David H. Shen ,  James Burnham ,  Ali Tabatabaei ,  Ann P. Shen

发明人： David H. Shen ,  James Burnham ,  Ali Tabatabaei ,  Ann P. Shen

IPC分类号： H03F3/68 ,  H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03F2203/45638 ,  H03F2203/7209

摘要： Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

摘要翻译： 共享一个或多个负载电感器包括在第一放大器的第一端接收第一输入信号，并使用第一放大器放大第一输入信号。 第一放大器耦合到第一放大器的第二端处的一个或多个负载电感器，并且耦合到第一放大器的第三端处的一个或多个专用源电感器。 此外，在第二放大器的第一端处接收第二输入信号，该第二放大器使用第二放大器放大第二输入信号。 第二放大器耦合到第二放大器的第二端处的一个或多个负载电感器，并且耦合到第二放大器的第三端处的一个或多个专用源电感器。

公开(公告)号：US20090085545A1

公开(公告)日：2009-04-02

申请号：US12175316

申请日：2008-07-17

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： G05F1/565

CPC分类号： G05F1/565

摘要： In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode.

摘要翻译： 在一些实施方式中，系统包括能够在三种功率模式之间切换的低功率稳压器：电源关闭模式，低功率模式和较高功率模式。 该系统包括耦合到电压调节器以在低功率模式和较高功率模式之间切换的选择器，以及在功率关断模式和低功率或更高功率模式之间切换的开关。 该系统还具有控制电路，用于控制开关和选择器，以控制三种功率模式中的任何一种电压调节器的工作。 在低功率模式下，电压调节器中使用的总电流为微安或纳秒级。 低功耗模式下的电压调节器在较高功率模式下具有比电压调节器低两到几个数量级的低电流使用。