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    High speed non-volatile electronic memory configuration
    3.
    发明授权
    High speed non-volatile electronic memory configuration 有权
    高速非易失性电子内存配置

    公开(公告)号：US07315951B2

    公开(公告)日：2008-01-01

    申请号：US10811913

    申请日：2004-03-30

    申请人： Paul Hanrieder ,  Marc L. Graves ,  Ken R. M. Hambly

    发明人： Paul Hanrieder ,  Marc L. Graves ,  Ken R. M. Hambly

    IPC分类号： G06F1/00 ,  G06F11/30

    CPC分类号： G06F1/30 ,  G11C5/143 ,  G11C7/24

    摘要： A high speed non-volatile electronic memory configuration and method is disclosed. In one particular exemplary embodiment, the high speed non-volatile electronic memory configuration may be realized comprising a high speed volatile memory, a non-volatile memory coupled to the high speed volatile memory, a controller coupled to the high speed volatile memory and the non-volatile memory, and a power level detector that detects when power is above a particular minimum operating voltage level. The controller monitors data storage changes made within the high speed volatile memory and controls the transfer of stored data from the high speed volatile memory to the non-volatile memory, and vice-versa, when power is above the particular minimum operating voltage level.

    摘要翻译： 公开了一种高速非易失性电子存储器配置和方法。 在一个特定的示例性实施例中，可以实现高速非易失性电子存储器配置，其包括高速易失性存储器，耦合到高速易失性存储器的非易失性存储器，耦合到高速易失性存储器的控制器和非易失性存储器， 以及功率电平检测器，用于检测功率高于特定的最低工作电压电平。 控制器监视在高速易失性存储器内进行的数据存储改变，并且当电力高于特定的最低工作电压电平时控制从高速易失性存储器向非易失性存储器传送所存储的数据，反之亦然。

    CAPTURING QUALITY OF SERVICE
    6.
    发明申请
    CAPTURING QUALITY OF SERVICE 无效
    承担服务质量

    公开(公告)号：US20020091636A1

    公开(公告)日：2002-07-11

    申请号：US09276207

    申请日：1999-03-25

    申请人： NORTEL NETWORKS CORPORATION

    发明人： WILLIAM CARTER CARROLL BULLARD

    IPC分类号： G06F017/60

    CPC分类号： H04L12/1403 ,  G06Q20/102 ,  H04L12/14 ,  H04L12/1485 ,  H04L43/00 ,  H04L43/0811 ,  H04L43/0829 ,  H04L43/10

    摘要： A system for collecting and aggregating data from network entities for a data consuming application is described. The system includes a data collector layer to receive network flow information from the network entities and to produce records based on the information. The system also includes a flow aggregation layer fed from the data collection layer and coupled to a storage device. The flow aggregation layer receiving records produced by the data collector layer and aggregates received records. The system can also include an equipment interface layer coupled to the data collector layer and a distribution layer to obtain selected information stored in the storage device and to distribute the select information to a requesting, data consuming application.

    摘要翻译： 描述用于从数据消费应用的网络实体收集和聚合数据的系统。 该系统包括数据收集器层，用于从网络实体接收网络流信息，并根据该信息产生记录。 该系统还包括从数据收集层馈送并耦合到存储设备的流聚合层。 流聚合层接收由数据收集器层产生的记录并聚合接收的记录。 该系统还可以包括耦合到数据收集器层的设备接口层和分布层，以获得存储在存储设备中的选定信息并将选择信息分发到请求的数据消耗应用。

    Method and apparatus for enhanced partial packet discard
    8.
    发明授权
    Method and apparatus for enhanced partial packet discard 失效
    增强部分分组丢弃的方法和装置

    公开(公告)号：US6151299A

    公开(公告)日：2000-11-21

    申请号：US898463

    申请日：1997-07-24

    申请人： Norman Allan Lyon ,  Gregory Lloyd King ,  Ra'ed Yousif Awdeh

    发明人： Norman Allan Lyon ,  Gregory Lloyd King ,  Ra'ed Yousif Awdeh

    IPC分类号： H04L12/56

    CPC分类号： H04L49/9078 ,  H04L12/5602 ,  H04L12/5693 ,  H04L47/54 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/5648

    摘要： In an enhanced partial packet discard (PPD) methodology, if an end-of-packet cell is discarded for non-PPD reasons, all non-end-of-packet cells of the immediately following packet are discarded. When an end-of-packet cell may validly be discarded, a switch faced with an end-of-packet cell may discard that cell if the last cell admitted to the buffer was an end-of-packet cell. To reduce the likelihood of having to drop end-of-packet cells, a buffer is configured to include a partial packet discard threshold such that the buffer space between that threshold and the end of the buffer is reserved for use by end-of-packet cells.

    摘要翻译： 在增强的部分分组丢弃（PPD）方法中，如果由于非PPD原因而丢弃分组末端小区，则丢弃紧随其后的分组的所有非最终分组小区。 当分组终端小区可能被有效地丢弃时，如果允许缓冲器的最后一个小区是分组终端小区，则面向分组末端小区的交换机可以丢弃该小区。 为了减少必须丢弃分组末端单元的可能性，缓冲器被配置为包括部分分组丢弃阈值，使得该阈值和缓冲器结束之间的缓冲区空间被保留以供分组结束使用 细胞。

    Digital phase detector with ring oscillator capture and inverter delay calibration
    9.
    发明授权
    Digital phase detector with ring oscillator capture and inverter delay calibration 失效
    具有环形振荡器捕捉和逆变器延迟校准的数字相位检测器

    公开(公告)号：US6148052A

    公开(公告)日：2000-11-14

    申请号：US988391

    申请日：1997-12-10

    申请人： Wladyslaw Bogdan

    发明人： Wladyslaw Bogdan

    IPC分类号： G01R25/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/18 ,  H03D3/24

    CPC分类号： G01R25/00 ,  H03L7/085 ,  H03L7/18 ,  H03L7/087

    摘要： A DPD (digital phase error) circuit for measuring the phase skew between a first and a second clock signal for use in a variety of control systems and more particularly for use in DPLL (digital phase-locked loop) synchronizers. The DPD includes an ROG (ring oscillator generator) which has a string of inverter gates forming an RO (ring oscillator) and a ring counter. The ring counter operates to monitor the time elapsed from the occurrence of a reset clock signal edge by recording the number of oscillation periods of the RO. The RO and ring counter are coupled to an ROC (ring oscillator capture) unit which operates to capture the state of the RO and ring counter for every occurrence of a respective first clock signal edge and second clock signal edge so as to accurately evaluate the time elapsed since the occurrence of the preceding reset clock signal edge. These measurements are routed to a CU (control unit) where they are processed to determine the actual phase error between the first and second clock signals. For each capture effected in the ROC, a highly accurate calibration signal generated to have a fixed phase deviation from the reset clock signal is received for capturing state of the RO and ring counter to determine the average inverter propagation delay of the inverter gates forming the RO and accordingly calibrate each phase error in accordance with the proper average inverter propagation delay.

    摘要翻译： DPD（数字相位误差）电路，用于测量第一和第二时钟信号之间的相位偏差，用于各种控制系统，更具体地用于DPLL（数字锁相环）同步器。 DPD包括一个ROG（环形振荡器发生器），其具有形成RO（环形振荡器）的反相器门串和环形计数器。 振铃计数器通过记录RO的振荡周期数来监视从复位时钟信号沿发生的时间。 RO和环形计数器耦合到ROC（环形振荡器捕获）单元，其操作以在相应的第一时钟信号边缘和第二时钟信号边缘的每次出现时捕获RO和环形计数器的状态，以便准确地评估时间 自从出现上一个复位时钟信号边沿以来经过。 这些测量被路由到CU（控制单元），在那里处理它们以确定第一和第二时钟信号之间的实际相位误差。 对于在ROC中进行的每次捕获，接收到产生与复位时钟信号具有固定相位偏差的高精度校准信号以捕获RO和环形计数器的状态，以确定形成RO的反相器门的平均逆变器传播延迟 因此根据适当的平均逆变器传播延迟来校准每个相位误差。

    Method and system for managing forward link power control within a code-division multiple access mobile telephone communication network
    10.
    发明授权
    Method and system for managing forward link power control within a code-division multiple access mobile telephone communication network 失效
    用于在码分多址移动电话通信网络内管理前向链路功率控制的方法和系统

    公开(公告)号：US6144841A

    公开(公告)日：2000-11-07

    申请号：US37603

    申请日：1998-03-10

    申请人： Michael Stephen Feeney

    发明人： Michael Stephen Feeney

    IPC分类号： H04B7/005 ,  H04Q7/22 ,  H04B1/02

    CPC分类号： H04W52/283 ,  H04W52/282 ,  H04W52/362 ,  H04W52/20

    摘要： A method for managing forward link power control within a code-division multiple access mobile telephone communication network is disclosed. A mobile telephone communication network constantly monitors for a frame erasure reported by a mobile telephone. In response to the detection of a frame erasure, the mobile telephone's digital gain assigned to the mobile telephone by the mobile telephone communication network is increased by a step-up value to close the forward link. This step-up value may be different each time depending on the speed and position of the mobile telephone. Afterwards, the digital gain is continuously reduced in an exponential manner until another frame erasure is reported.

    摘要翻译： 公开了一种用于在码分多址移动电话通信网络内管理前向链路功率控制的方法。 移动电话通信网络不断监视移动电话报告的帧擦除。 响应于帧擦除的检测，由移动电话通信网络分配给移动电话的移动电话的数字增益增加了升压值以关闭前向链路。 每次取决于移动电话的速度和位置，该升压值可能是不同的。 之后，数字增益以指数方式连续减少，直到报告另一帧消除。