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公开(公告)号：US06934202B2
公开(公告)日：2005-08-23
申请号：US10345843
申请日：2003-01-16
申请人： Richard Ferrant
发明人： Richard Ferrant
CPC分类号： G11C29/848
摘要： The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.
摘要翻译： 本发明涉及一种集成电路，其包括至少一个相同元件的矩阵网络，能够至少在第一方向上被单独地寻址，并且至少包括至少对于该第一方向至少一个冗余元件，以及可逆地抑制 故障元件的操作并通过使用冗余元件来维持电路操作。 集成电路还可以包括绝对地禁止故障元件的操作并且通过使用冗余元件来维持电路操作的电路。
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公开(公告)号：US6147566A
公开(公告)日：2000-11-14
申请号：US995667
申请日：1997-12-22
CPC分类号： H02M3/073 , H03K3/0315
摘要： An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals. First and second RC type circuits produce the first and second driving signals to control the transitions in the third and fourth logic signals. The oscillator circuit can be used in a switch-over control circuit for a load pump type of high-voltage generator.
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3.发明授权System for providing a regulated voltage during abrupt variations in current 失效用于在电流突然变化期间提供稳压电压的系统
公开(公告)号：US6137275A
公开(公告)日：2000-10-24
申请号：US89783
申请日：1998-06-03
申请人： Jean-Michel Ravon
发明人： Jean-Michel Ravon
摘要： The present invention relates to a system for providing a regulated voltage meant to supply a load, including a source for providing a substantially constant current approximately corresponding to the maximum current likely to be surged by the load, and a device receiving the constant current and regulating the load supply voltage, at least one capacitor being connected between an output terminal of the regulation device and the ground.
摘要翻译： 本发明涉及一种用于提供用于提供负载的稳压电压的系统，包括用于提供基本上恒定的电流的源，所述电流大致对应于可能被负载激励的最大电流，以及接收恒定电流和调节 负载电源电压，至少一个电容器连接在调节装置的输出端子和地之间。
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公开(公告)号：US6114743A
公开(公告)日：2000-09-05
申请号：US390891
申请日：1999-09-07
申请人： Yvon Gris
发明人： Yvon Gris
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/10 , H01L29/165 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/0804 , H01L29/1004
摘要： The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.
摘要翻译： 本发明涉及一种包括横向阱隔离双极晶体管的集成电路。 绝缘阱的上部内周的第一部分是中空的，并且填充有与晶体管基底相同导电类型的多晶硅，以形成基极接触区域。 绝缘阱的上部内周的第二部分是中空的，并且填充与晶体管发射极具有相同导电类型的多晶硅，以形成发射极接触区域。
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公开(公告)号：US6107664A
公开(公告)日：2000-08-22
申请号：US891774
申请日：1997-07-14
摘要： A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.
摘要翻译： 静态自锁微型断路器包括：第一类型的第一MOS耗尽型晶体管，其通过其漏极连接到第一主端子，并且其栅极连接到第二主端子，第二类型的第二MOS耗尽型晶体管通过其第 漏极到第二主端子并通过其源极到第一晶体管的源极，第一类型的第三MOS耗尽晶体管通过其漏极连接到第一主端子，通过其栅极连接到第二主端子，并且由其源极 到第二晶体管的栅极。
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6.发明授权Electrical programmable non-volatile memory integrated circuit with option configuration register 失效带可选配置寄存器的电气可编程非易失性存储器集成电路
公开(公告)号：US6104634A
公开(公告)日：2000-08-15
申请号：US87415
申请日：1998-05-29
申请人： Laurent Rochard
发明人： Laurent Rochard
摘要： An electrically programmable non-volatile memory integrated circuit includes: read/write resources; a first bit line; a second bit line; an option configuration register consisting of at least one bit; a reading mechanism; and a writing mechanism. The option configuration register includes, for the at least one bit: a bistable element including at least one memory cell, and a static memory element. The at least one memory cell is coupled to the first bit line and to the second bit line, and the static memory element is coupled to the bistable element. The reading mechanism is for reading a state of the static memory element, and it utilizes the first and second bit lines and the read/write resources. The writing mechanism is for setting the state of the static memory element, and it utilizes the first and second bit lines and the read/write resources.
摘要翻译： 电可编程非易失性存储器集成电路包括：读/写资源; 第一个位线 第二位线 一个选项配置寄存器，由至少一个位组成; 阅读机制; 和写作机制。 对于至少一个位，选项配置寄存器包括：包括至少一个存储器单元的双稳态元件和静态存储器元件。 至少一个存储器单元耦合到第一位线和第二位线，并且静态存储器元件耦合到双稳态元件。 读取机制用于读取静态存储器元件的状态，并且它利用第一和第二位线以及读/写资源。 写入机制用于设置静态存储器元件的状态，并且它利用第一和第二位线以及读/写资源。
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公开(公告)号：US6101564A
公开(公告)日：2000-08-08
申请号：US690985
申请日：1996-08-01
CPC分类号： G06F13/18
摘要： This invention relates to a device for organizing access to a bus connecting a memory to at least two entities issuing asynchronous binary signals representing requests for access to the bus. The device supplies binary signals to authorize the access to an entity based on a priority determination between the different requests and includes a priority decoder in wired logic associated with an input register. A loading of the state of the access request signals happens, if an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal issued by a memory controller associated with the memory and indicative of the end of a memory cycle.
摘要翻译： 本发明涉及一种用于组织对总线的访问的设备，该总线将存储器连接到发出表示对总线访问的请求的异步二进制信号的至少两个实体。 该设备提供二进制信号以根据不同请求之间的优先级确定授权对实体的访问，并且包括与输入寄存器相关联的有线逻辑中的优先级解码器。 当存储器的读或写周期执行时存在访问请求信号的状态的加载，当脉冲到由存储器关联的存储器控制器发出的信号和指示 的记忆周期结束。
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公开(公告)号：US06097446A
公开(公告)日：2000-08-01
申请号：US863660
申请日：1997-05-27
申请人： Michel Imbert , Serge Volmier , Xavier Cauchy
发明人： Michel Imbert , Serge Volmier , Xavier Cauchy
CPC分类号： H04N7/56 , H04N21/440218 , H04N5/4401
摘要： The present invention relates to a method for regulating, in the read mode, memory areas of a circuit for decompressing a video data flow compressed according to an MPEG standard, with respect to the writing rate of the compressed data flow into the memory areas, the decompression circuit issuing a flow of image data at the rate of signals for horizontally and vertically synchronizing the images issued by a circuit for coding according to a color television standard, this method including generating a clock signal having a fixed frequency for reading from the memory areas and for generating the horizontal and vertical synchronization signals, and shifting the occurrence of an edge triggering the vertical synchronization signal based on a signal indicative of the state of a buffer memory associated with the memory areas.
摘要翻译： 本发明涉及一种用于在读取模式下调节用于解压缩根据MPEG标准压缩的视频数据流的电路的存储区域，该方法关于压缩数据流到存储区域的写入速率， 解压缩电路以按照彩色电视标准的用于水平和垂直同步用于编码的电路的图像的信号速率发出图像数据流，该方法包括产生具有固定频率的时钟信号以从存储区域读取 并且用于产生水平和垂直同步信号，并且基于指示与存储器区域相关联的缓冲存储器的状态的信号来移动触发垂直同步信号的边沿的出现。
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公开(公告)号：US6084389A
公开(公告)日：2000-07-04
申请号：US955183
申请日：1997-10-21
CPC分类号： G05F1/59
摘要： The present invention relates to a voltage regulator including at least one input terminal for receiving a supply voltage; a circuit for generating a reference voltage proportional to a desired regulated output voltage; an amplifier of a signal of error between the reference voltage and the output voltage assigned with a coefficient of proportionality; a capacitor connected between an output terminal and the ground, further including means for supplying at least the circuit and the amplifier with the output voltage in case of a deficiency or a disappearing of the supply voltage present on the input terminal.
摘要翻译： 本发明涉及一种电压调节器，其包括用于接收电源电压的至少一个输入端子; 用于产生与期望的调节输出电压成比例的参考电压的电路; 基准电压与分配比例系数的输出电压之间的误差信号的放大器; 连接在输出端子和地之间的电容器，还包括用于在输入端子上存在电源电压不足或消失的情况下至少向电路和放大器提供输出电压的装置。
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公开(公告)号：US6052290A
公开(公告)日：2000-04-18
申请号：US184923
申请日：1998-11-02
申请人： Jean-Michel Moreau
发明人： Jean-Michel Moreau
CPC分类号： H02M1/4258 , H02M3/335 , Y02B70/126 , Y02P80/112
摘要： A circuit for providing a rectified voltage to a flyback switch-mode supply circuit comprises a rectifying bridge having output terminals; a primary winding of the switch-mode supply having an intermediate tap; a switch serially connected with the primary winding; the serial connection between the output terminals, of a first diode and a capacitor, the first diode being biased so as to allow the charging of the capacitor; a second diode between a first output terminal of the winding, the second and third diodes being biased so as to let the current flow towards a second terminal of the winding.
摘要翻译： 用于向回扫开关模式电源电路提供整流电压的电路包括具有输出端的整流桥; 具有中间抽头的开关模式电源的初级绕组; 与初级绕组串联连接的开关; 第一二极管和电容器的输出端子之间的串联连接，第一二极管被偏置以允许电容器的充电; 绕组的第一输出端之间的第二二极管，第二和第三二极管被偏置以使电流流向绕组的第二端。
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