-
1.发明授权公开(公告)号：US12127487B2
公开(公告)日：2024-10-22
申请号：US18058337
申请日：2022-11-23
申请人： TetraMem Inc.
发明人： Minxian Zhang , Ning Ge
CPC分类号： H10N70/826 , H10B63/80 , H10N70/841 , H10N70/8833
摘要： The present disclosure provides an apparatus, including: a substrate; a bottom electrode formed on the substrate; a first base oxide layer formed on the bottom electrode; a first geometric confining layer formed on the first base oxide layer, wherein the first geometric confining layer comprises a first plurality of pin-holes; a second base oxide layer formed on the first geometric confining layer and connected to a first top surface of the first base oxide layer via the first plurality of pin-holes; and a top electrode formed on the second base oxide layer. The first base oxide layer includes TaOx, HfOx, TiOx, ZrOx, or a combination thereof. The first geometric confining layer comprises Al2O3, SiO2, Si3N4, Y2O3, Gd2O3, Sm2O3, CeO2, Er2O3, or a combination thereof.
-
公开(公告)号：US11985911B2
公开(公告)日：2024-05-14
申请号：US17651790
申请日：2022-02-19
申请人： TetraMem Inc.
发明人： Minxian Zhang , Ning Ge
CPC分类号： H10N70/841 , H10B63/80 , H10N70/023 , H10N70/8833
摘要： Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.
-
公开(公告)号：US20240137038A1
公开(公告)日：2024-04-25
申请号：US18156171
申请日：2023-01-18
申请人： TetraMem Inc.
发明人： Ning Ge , Hengfang Zhu , Sangsoo Lee , Wenbo Yin
IPC分类号： H03M1/36
CPC分类号： H03M1/365
摘要： The present disclosure provides a voltage divider circuit utilizing non-volatile memory devices. The non-volatile memory device may include, for example, a memristor device, an MRAM (Magnetoresistive random access memory) device, a phase-change memory (PCM) device, a floating gate, a spintronic device, etc. The voltage divider circuit may include one or more first non-volatile memory devices that form a resistor ladder. The resistor ladder may produce a plurality of reference voltages when the resistor ladder is connected between two voltages.
-
公开(公告)号：US20230102234A1
公开(公告)日：2023-03-30
申请号：US18060420
申请日：2022-11-30
申请人： TetraMem Inc.
发明人： Ning Ge
摘要： The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.
-
公开(公告)号：US20230088575A1
公开(公告)日：2023-03-23
申请号：US18052700
申请日：2022-11-04
申请人： TetraMem Inc.
发明人： Ning Ge
摘要： Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.
-
公开(公告)号：US11610942B2
公开(公告)日：2023-03-21
申请号：US17357341
申请日：2021-06-24
申请人： TetraMem Inc.
发明人： Ning Ge
摘要： Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line, a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.
-
公开(公告)号：US11539906B2
公开(公告)日：2022-12-27
申请号：US16702444
申请日：2019-12-03
申请人： TETRAMEM INC.
IPC分类号： H04N5/3745 , G11C13/00 , H04N5/378
摘要： Technologies relating to CMOS image sensors with integrated Resistive Random-Access Memory (RRAMs) units that provide energy efficient analog storage, ultra-high speed analog storage, and in-memory computing functions are disclosed. An example CMOS image sensor with integrated RRAM crossbar array circuit includes a CMOS image sensor having multiple pixels configured to receive image signals; a column decoder configured to select the pixels in columns to read out; a row decoder configured to select the pixels in rows to read out; an amplifier configured to amplify first signals received from the CMOS image sensor; a multiplexer configured to sequentially or serially read out second signals received from the amplifier; and a first RRAM crossbar array circuit configured to store third signals received from the multiplexer.
-
公开(公告)号：US11539370B2
公开(公告)日：2022-12-27
申请号：US16798397
申请日：2020-02-23
申请人： TETRAMEM INC.
发明人： Ning Ge
摘要： Technologies relating to analog-to-analog quantizers with an intrinsic Rectified Linear Unit (ReLU) function designed for in-memory computing are disclosed. An apparatus, in some implementations, includes: a DAC; a first crossbar connected to the DAC; a first analog quantizer connected to the first crossbar; a buffer connected to the first analog quantizer; a second crossbar connected to the buffer; and an ADC connected to the second crossbar.
-
9.发明授权公开(公告)号：US11531728B2
公开(公告)日：2022-12-20
申请号：US16805764
申请日：2020-02-29
申请人： TETRAMEM INC.
发明人： Ning Ge
摘要： Technologies relating to implementing two-stage ramp ADCs in crossbar array circuits for high performance matrix multiplication are disclosed. An example two-stage ramp ADC includes: a transimpedance amplifier configured to convert an input signal from current to voltage; a comparator connected to the transimpedance amplifier; a switch bias set connected to the comparator; a switch side capacitor in parallel with the switch bias set; a ramp side capacitor in parallel with the switch bias set; a ramp generator connected to the comparator via the ramp side capacitor, wherein the ramp generator is configured to generate a ramp signal; a counter; and a memory connected to the comparator, wherein the memory is configured to store an output of the comparator.
-
公开(公告)号：US20220130902A1
公开(公告)日：2022-04-28
申请号：US16550258
申请日：2019-08-25
申请人： TETRAMEM INC.
摘要： Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a first NMOS transistor; a second PMOS transistor; and an RRAM device. The first NMOS transistor and the second PMOS transistor are in parallel as a pair, wherein the pair connects in series with the RRAM device. The apparatus may further include an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal.
-
-
-
-
-
-
-
-
-
搜索结果
94 条记录 (耗时 0.019 秒)
