公开(公告)号：US20090201185A1

公开(公告)日：2009-08-13

申请号：US12028104

申请日：2008-02-08

申请人： Honglei Wu

发明人： Honglei Wu

IPC分类号： H03M1/10

CPC分类号： H03M1/182

摘要： An analog-to-digital conversion circuit and a method for calibrating an analog-to-digital conversion circuit are provided. A digital translation of an analog voltage is analyzed to determine a characteristic value of the analog voltage. A reference voltage, with which the digital translation is generated, is set to a value that is a minimum amount greater than the characteristic value. Additional embodiments include setting an offset voltage, with which the digital translation is also generated.

摘要翻译： 提供了一种用于校准模数转换电路的模拟 - 数字转换电路和方法。 分析模拟电压的数字转换，以确定模拟电压的特征值。 将产生数字转换的参考电压设置为大于特征值的最小量的值。 另外的实施例包括设置也产生数字转换的偏移电压。

公开(公告)号：US07532077B2

公开(公告)日：2009-05-12

申请号：US11801199

申请日：2007-05-08

申请人： Stanley Wang ,  Thomas H. Lee

发明人： Stanley Wang ,  Thomas H. Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/199 ,  H03L7/0891 ,  H03L7/10

摘要： A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.

摘要翻译： 一种频率合成器（50,70），包括用于在启动之前禁用频率合成器（50,70）的元件的边缘检测电路（51,60）。 边缘检测电路检测频率合成器（50,70）的参考时钟信号（ref_clk）的过渡沿，并且在检测到过渡边缘时使能频率合成器（50,70）的元件。

公开(公告)号：US20090043957A1

公开(公告)日：2009-02-12

申请号：US12042384

申请日：2008-03-05

申请人： Paul G. Davis

发明人： Paul G. Davis

IPC分类号： G06F12/00

CPC分类号： G11C15/00 ,  G11C29/846

摘要： A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address. When address requests are received thereafter, CAM circuit 200 compares the address request to its stored direct addresses. If a match is found the paired emulation address is passed through multiplexer 201 instead of the direct address. As a result, the substitute or upgraded data in configurable memory 203 is output to data bus 205 in place of the old data.

摘要翻译： 一种通过使用具有内容寻址存储器（CAM）的存储器仿真电路作为仿真电路仲裁器的智能部分来提供现场更新的方法。 CAM电路200由可配置存储器组成，并且最初未被编程。 地址请求直接通过多路复用器201到只读存储器（ROM）202.结果，ROM 202中对应于所请求的地址的数据位置中的数据将被输出到数据总线205.如果ROM 202中的数据位置变成 缺陷或包含需要升级的数据，电路实现重新映射数据位置。 CAM电路200被编程为在ROM 202中要被替换的直接地址。直接地址与可配置存储器203中的数据位置的仿真地址配对。升级的或替换的数据在配对的仿真地址被编程到可配置存储器203中。 当其后接收到地址请求时，CAM电路200将地址请求与其存储的直接地址进行比较。 如果发现匹配，则配对仿真地址通过多路复用器201而不是直接地址。 结果，可配置存储器203中的替代或升级的数据被输出到数据总线205，而不是旧的数据。

公开(公告)号：US20080169866A1

公开(公告)日：2008-07-17

申请号：US11653570

申请日：2007-01-16

申请人： Bendik Kleveland ,  Thomas H. Lee

发明人： Bendik Kleveland ,  Thomas H. Lee

IPC分类号： G05F1/10 ,  G05F3/16

CPC分类号： G05F3/30

摘要： A combined charge storage and bandgap reference is disclosed. In one embodiment, a system comprises a bandgap reference circuit; a charge storage circuit, wherein an output of the bandgap reference circuit is provided as an input to the charge storage circuit; and a control circuit in communication with the bandgap reference circuit and the charge storage circuit. The control circuit is operative to control charging of the charge storage circuit by the output of the bandgap reference circuit and control selection of one of the output of the bandgap reference circuit and an output of the charge storage circuit. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

摘要翻译： 公开了组合的电荷存储和带隙基准。 在一个实施例中，系统包括带隙基准电路; 电荷存储电路，其中所述带隙基准电路的输出被提供给所述电荷存储电路的输入; 以及与带隙基准电路和电荷存储电路连通的控制电路。 该控制电路用于通过带隙参考电路的输出控制电荷存储电路的充电，并控制对带隙基准电路的输出之一和电荷存储电路的输出的选择。 公开了其它实施例，并且每个实施例可以单独使用或组合使用。

公开(公告)号：US20090296853A1

公开(公告)日：2009-12-03

申请号：US12129681

申请日：2008-05-30

申请人： Meng-Chang Doong ,  Jia-Yi Chen ,  Thomas Lee

发明人： Meng-Chang Doong ,  Jia-Yi Chen ,  Thomas Lee

IPC分类号： H04L25/03

CPC分类号： H04L25/03834 ,  H04L27/2007

摘要： A transmitter architecture and method of modulation that include a rotation-direction control circuit for varying the direction of rotation of phase transitions of a phase modulation based on the occurrence of a predetermined pattern of input data. This variation of rotation direction by the rotation-direction control circuit maintains the output spectrum of a modulated signal within the spectral mask requirements of an associated communications standard and thereby enables the use of non-linear power amplifiers in applications that generally require linear amplifiers.

摘要翻译： 一种发射机结构和调制方法，其包括用于基于输入数据的预定模式的出现来改变相位调制的相变的旋转方向的旋转方向控制电路。 通过旋转方向控制电路的旋转方向的这种变化将调制信号的输出频谱维持在相关通信标准的频谱掩模要求内，从而使得能够在通常需要线性放大器的应用中使用非线性功率放大器。

公开(公告)号：US20090278517A1

公开(公告)日：2009-11-12

申请号：US12118773

申请日：2008-05-12

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： G05F1/563

CPC分类号： G05F1/563 ,  H02M3/1584 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16

摘要： A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.

摘要翻译： 提供了一种电压调节器装置和附带的方法，用于向电子设备提供有效的电压调节。 高效调节器400从节点VIN处的电池或其他电源接收VIN上的输入电压，并在节点VOUT向负载装置404提供稳定的调节电压。 负载装置404拉动不同量的电流，并且根据其工作条件对VOUT上的电压需要不同程度的容差。 数据收集和控制电路401能够启用和禁用调节器402和调节器403.数据收集和控制电路401还能够测量与负载设备404相关联的某些性能参数和负载设备404的操作条件。数据收集和控制 如果所述操作条件使得当数据收集和控制电路401启用调节器403时，与加载404相关联的性能参数低于预定标准，则电路401使得调节器402能够启用调节器402。

公开(公告)号：US07560983B1

公开(公告)日：2009-07-14

申请号：US12025005

申请日：2008-02-02

申请人： Susan Luschas ,  Thomas H. Lee

发明人： Susan Luschas ,  Thomas H. Lee

IPC分类号： H03F3/68

CPC分类号： H03F1/0277 ,  H03F1/56 ,  H03F3/24 ,  H03F3/72 ,  H03F2200/387 ,  H03F2203/7236

摘要： An amplifier circuit and method for amplifying a signal efficiently over a plurality of power ranges. The amplifier circuit including a strong amplifier which is efficient over a first power range and a weak amplifier which is efficient over a second power range. An impedance transformation circuit is used for generating a higher potential and providing increased efficiency when the second range of power is present. A circuit biases active the strong amplifier when the first power range of is present and biases active the weak amplifier when the second power range is present.

摘要翻译： 一种用于在多个功率范围上有效放大信号的放大器电路和方法。 该放大器电路包括在第一功率范围内有效的强放大器和在第二功率范围内有效的弱放大器。 当存在第二功率范围时，阻抗变换电路用于产生更高的电位并提供增加的效率。 当存在第一功率范围时，电路偏置激活强放大器，并在存在第二功率范围时偏置弱放大器。

公开(公告)号：US20090054004A1

公开(公告)日：2009-02-26

申请号：US11841825

申请日：2007-08-20

申请人： Yuen Hui Chee ,  Thomas H. Lee

发明人： Yuen Hui Chee ,  Thomas H. Lee

IPC分类号： H04B1/38 ,  H03F3/04

CPC分类号： H03F1/301 ,  H03F3/193 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2203/45244 ,  H03F2203/45386 ,  H03F2203/45596

摘要： A biasing scheme for compensating for a difference in biasing currents between a first circuit element (10) and second circuit element (32) in a stacked circuit configuration. A current-difference source (38) generates a difference current that is substantially equal to the difference between the biasing currents of the first circuit element (10) and second circuit element (32) in order to compensate for process, temperature and supply variations.

摘要翻译： 一种偏置方案，用于补偿堆叠电路配置中的第一电路元件（10）和第二电路元件（32）之间的偏置电流的差。 电流差源（38）产生基本上等于第一电路元件（10）和第二电路元件（32）的偏置电流之间的差的差电流，以便补偿过程，温度和电源变化。

公开(公告)号：US20080084919A1

公开(公告)日：2008-04-10

申请号：US11606448

申请日：2006-11-30

申请人： Bendik Kleveland ,  David Friedman ,  Stanley B-T Wang ,  Thomas H. Lee ,  Carl Gyllenhammer

发明人： Bendik Kleveland ,  David Friedman ,  Stanley B-T Wang ,  Thomas H. Lee ,  Carl Gyllenhammer

IPC分类号： H04B1/00

CPC分类号： H04B1/707 ,  H04B1/692

摘要： In a wireless transmission method, an input data signal corresponding to a serial combination of a first transmit data signal and a second transmit data signal is received. The first and second transmit data signals are phase-modulated with different first and second spreading code signals to produce first and second DSSS transmit signals, which are serially output as a baseband transmit signal that is up-converted to a selected wireless transmission frequency range. The first and second phase-modulated signals are serially output as a baseband transmit signal. In a wireless reception method, an input receive signal is down-converted to a baseband receive signal corresponding to a serial combination of first and second time-interleaved DSSS receive signals in a baseband frequency range. The first and second DSSS receive signals are phase-demodulated with different first and second de-spreading code signals to produce first and second receive data signals.

摘要翻译： 在无线发送方法中，接收对应于第一发送数据信号和第二发送数据信号的串行组合的输入数据信号。 第一和第二发射数据信号用不同的第一和第二扩展码信号进行相位调制，以产生第一和第二DSSS发射信号，其被串行地输出为上变频到所选无线传输频率范围的基带发射信号。 串行输出第一和第二相位调制信号作为基带发送信号。 在无线接收方法中，将输入接收信号下变频为与基带频率范围内的第一和第二时间交织的DSSS接收信号的串行组合相对应的基带接收信号。 第一和第二DSSS接收信号用不同的第一和第二去扩展码信号进行相位解调，以产生第一和第二接收数据信号。

公开(公告)号：US20090206894A1

公开(公告)日：2009-08-20

申请号：US12032689

申请日：2008-02-17

申请人： Stanley Bo-Ting Wang ,  Meng-Chang Doong

发明人： Stanley Bo-Ting Wang ,  Meng-Chang Doong

IPC分类号： H03L7/085 ,  H03L7/099

CPC分类号： H03L7/08 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

摘要： A phase-locked loop capable of being dynamically configured to optimize phase-noise performance during different modes of operation. The phase-locked loop may include a switchable charge pump, loop filter and voltage-controlled oscillator having auxiliary circuit components that may be switched in and out to achieve calibration settings for optimizing phase-noise performance for different modes of operation, while minimizing unnecessary power consumption, and without disturbing the stability of the phase-locked loop.

摘要翻译： 锁相环能够被动态地配置成在不同的操作模式下优化相位噪声性能。 锁相环可以包括可切换电荷泵，环路滤波器和压控振荡器，其具有可被切换和输出的辅助电路部件，以实现用于优化不同操作模式的相位噪声性能的校准设置，同时最小化不必要的功率 消耗，并且不影响锁相环的稳定性。