公开(公告)号：US06965162B2

公开(公告)日：2005-11-15

申请号：US10226539

申请日：2002-08-23

申请人： Makoto Yoshino ,  Kunio Sakamoto ,  Kensho Murata

发明人： Makoto Yoshino ,  Kunio Sakamoto ,  Kensho Murata

IPC分类号： H01L23/12 ,  H01L21/58 ,  H01L23/31 ,  H01L23/498 ,  H05K3/24 ,  H01L23/13

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2224/05599 ,  H01L2224/29012 ,  H01L2224/29101 ,  H01L2224/30131 ,  H01L2224/30133 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/24 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device designed to reduce the warp of a substrate due to curing contraction, etc. of an insulation pattern while forming the insulation pattern on the surface of a substrate so that it may be interposed between a semiconductor chip and a conductor pattern by offering a semiconductor chip mounting substrate equipped with a flexible substrate 11 (insulating film 16) having a chip mounting region 19 for mounting a semiconductor chip 13 via an adhesive 12, conductor patterns 20 that are formed on the surface of the above-mentioned substrate 11 and electrically connected to the semiconductor chip 13 in an external region of the above-mentioned chip mounting region 19, and an insulation pattern 21 formed on the surface of the substrate 11 and partially in the chip mounting region 19 so that it may be interposed between the semiconductor chip 13 and the conductor patterns 20.

摘要翻译： 一种半导体器件，其被设计用于在衬底的表面上形成绝缘图案的同时，由于绝缘图案的固化收缩等而减少衬底的翘曲，使得其可以通过提供半导体芯片和导体图案来插入到半导体芯片和导体图案之间 具有柔性基板11（绝缘膜16）的半导体芯片安装基板具有用于通过粘合剂12安装半导体芯片13的芯片安装区域19，形成在上述基板11的表面上的导体图案20， 连接到上述芯片安装区域19的外部区域中的半导体芯片13，以及形成在基板11的表面上并部分地在芯片安装区域19中的绝缘图案21，使得其可以插入在半导体 芯片13和导体图案20。

公开(公告)号：US20030039102A1

公开(公告)日：2003-02-27

申请号：US10226539

申请日：2002-08-23

发明人： Makoto Yoshino ,  Kunio Sakamoto ,  Kensho Murata

IPC分类号： H05K007/00

CPC分类号： H01L24/83 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2224/05599 ,  H01L2224/29012 ,  H01L2224/29101 ,  H01L2224/30131 ,  H01L2224/30133 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/24 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device designed to reduce the warp of a substrate due to curing contraction, etc. of an insulation pattern while forming the insulation pattern on the surface of a substrate so that it may be interposed between a semiconductor chip and a conductor pattern by offering a semiconductor chip mounting substrate equipped with a flexible substrate 11 (insulating film 16) having a chip mounting region 19 for mounting a semiconductor chip 13 via an adhesive 12, conductor patterns 20 that are formed on the surface of the above-mentioned substrate 11 and electrically connected to the semiconductor chip 13 in an external region of the above-mentioned chip mounting region 19, and an insulation pattern 21 formed on the surface of the substrate 11 and partially in the chip mounting region 19 so that it may be interposed between the semiconductor chip 13 and the conductor patterns 20.

摘要翻译： 一种半导体器件，其被设计用于在衬底的表面上形成绝缘图案的同时，由于绝缘图案的固化收缩等而减少衬底的翘曲，使得其可以通过提供半导体芯片和导体图案来插入到半导体芯片和导体图案之间 具有柔性基板11（绝缘膜16）的半导体芯片安装基板具有用于通过粘合剂12安装半导体芯片13的芯片安装区域19，形成在上述基板11的表面上的导体图案20， 连接到上述芯片安装区域19的外部区域中的半导体芯片13，以及形成在基板11的表面上并部分地在芯片安装区域19中的绝缘图案21，使得其可以插入在半导体 芯片13和导体图案20。