公开(公告)号：US06664722B1

公开(公告)日：2003-12-16

申请号：US09594874

申请日：2000-06-15

Applicant: Zvi Yaniv ,  Richard Lee Fink ,  Zhidan Li Tolt ,  Leif Thuesen

Inventor： Zvi Yaniv ,  Richard Lee Fink ,  Zhidan Li Tolt ,  Leif Thuesen

IPC: H01J113

CPC classification number: B82Y15/00 ,  B82Y10/00 ,  H01J1/304

Abstract: A carbon film having an area of insulating material surrounded by an area of conducing material, and an area of material between the area of insulating material and the area of conducting material having a graded dielectric constant which varies from high to low from the area of insulating material to the area of conducting material. An emission site on the carbon film will emit electrons as a function of time, and as a function of distance across an emission site area.

Abstract translation: 具有由导电材料区域包围的绝缘材料区域的碳膜，以及绝缘材料区域和导电材料区域之间的材料区域，其具有从绝缘区域的高低变化的梯度介电常数 材料到导电材料区域。 碳膜上的发射部位将作为时间的函数发射电子，并且作为发射场地区域的距离的函数。

公开(公告)号：US06522054B2

公开(公告)日：2003-02-18

申请号：US09435818

申请日：1999-11-08

Applicant: Masaaki Shibata

Inventor： Masaaki Shibata

IPC: H01J113

CPC classification number: H01J1/316 ,  H01J2329/00

Abstract: An electron-emitting device comprising a substrate, first and second carbon films disposed on the substrate, and first and second electrodes electrically connected to the first and second carbon films, respectively. The first and second carbon films are opposed to each other with a first gap interposed therebetween, and a portion of the substrate located between the electrodes comprises at least Si, O and N.

Abstract translation: 一种电子发射器件，包括衬底，设置在衬底上的第一和第二碳膜以及分别与第一和第二碳膜电连接的第一和第二电极。 第一和第二碳膜彼此相对并且间隔开第一间隙，并且位于电极之间的衬底的一部分至少包括Si，O和N.

公开(公告)号：US06736927B2

公开(公告)日：2004-05-18

申请号：US10167937

申请日：2002-06-10

Applicant: Albert Wang ,  Scott Baron ,  Prasad Padmanabhan ,  Gerald M. Cox

Inventor： Albert Wang ,  Scott Baron ,  Prasad Padmanabhan ,  Gerald M. Cox

IPC: H01J113

CPC classification number: G03F7/427 ,  H01L21/31138

Abstract: A system is disclosed for speeding workpiece thoughput in low pressure, high temperature semiconductor processing reactor. The system includes apparatus for loading a workpiece into a chamber at atmospheric pressure, bringing the chamber down to an intermediate pressure, and heating the wafer while under the intermediate pressure. The chamber is then pumped down to the operating pressure. The preferred embodiments involve single wafer plasma ashers, where a wafer is loaded onto lift pins at a position above a wafer chuck, the pressure is rapidly pumped down to about 40 Torr by rapidly opening and closing an isolation valve, and the wafer is simultaneously lowered to the heated chuck. Alternatively, the wafer can be pre-processed to remove an implanted photoresist crust at a first temperature and the chamber then backfilled to about 40 Torr for further heating to close to the chuck temperature. At 40 Torr, the heat transfer from the chuck to the wafer is relatively fast, but still slow enough to avoid thermal shock. In the interim, the pump line is further pumped down to operating pressure (about 1 Torr) behind the isolation valve. The chamber pressure is then again reduced by opening the isolation valve, and the wafer is processed.

Abstract translation: 公开了一种用于在低压，高温半导体处理反应器中加速工件加工的系统。 该系统包括用于在大气压力下将工件装载到室中的装置，使室降至中间压力，并在中间压力下加热晶片。 然后将腔室泵送到操作压力。 优选实施例涉及单晶片等离子体灰化器，其中将晶片加载到晶片卡盘上方位置的升降销上，通过快速打开和关闭隔离阀将压力快速泵送至约40托，同时降低晶片 到加热的卡盘。 或者，可以预先处理晶片以在第一温度下去除植入的光致抗蚀剂的外壳，然后将该腔重新填充至约40托，以进一步加热以接近卡盘温度。 在40乇时，从卡盘到晶片的热传递相对较快，但仍然足够慢以避免热冲击。 在此期间，泵管线进一步被泵送到隔离阀后面的工作压力（约1乇）。 然后通过打开隔离阀再次减小腔室压力，并且处理晶片。

公开(公告)号：US06590322B2

公开(公告)日：2003-07-08

申请号：US10012615

申请日：2001-12-12

Applicant: David S. Y. Hsu

Inventor： David S. Y. Hsu

IPC: H01J113

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01J1/304 ,  H01J1/3046 ,  H01J3/022 ,  H01J9/025 ,  H01J2201/30469 ,  H01J2201/319

Abstract: A field emitter cell includes a thin-film-edge emitter normal to the gate layer. The field emitter cell may include a conductive substrate layer, an insulator layer having a perforation, a gate layer having a perforation, an emitter layer, and other optional layers. The perforation in the gate layer is larger and concentrically offset with respect to the perforation in the insulating layer and may be of a tapered construction. Alternatively, the perforation in the gate layer may be coincident with, or larger or smaller than, the perforation in the insulating layer, provided that the gate layer is shielded from the emitter from a direct line-of-sight by a nonconducting standoff layer. Optionally, the thin-film-edge emitter may include incorporated nanofilaments. The field emitter cell has low gate current, making it useful for various applications such as field emitter displays, high voltage power switching, microwave, RF amplification and other applications that require high emission currents.

公开(公告)号：US06504292B1

公开(公告)日：2003-01-07

申请号：US09365059

申请日：1999-07-30

Applicant: Kyung Moon Choi ,  Sungho Jin ,  Gregory Peter Kochanski ,  Wei Zhu

Inventor： Kyung Moon Choi ,  Sungho Jin ,  Gregory Peter Kochanski ,  Wei Zhu

IPC: H01J113

CPC classification number: H01J9/025 ,  B82Y10/00 ,  H01J1/304 ,  H01J2201/30469 ,  Y10S977/745 ,  Y10S977/939

Abstract: In accordance with the invention, an improved conductive nanostructure assembly comprises an array of metallized nanostructures disposed on a conductive substrate. The substrate can also be metallized. Such assemblies provide continuous electron transport from the substrate to the tips of the nanostructures. Several ways of making such assemblies are described along with several devices employing the assemblies.

Abstract translation: 根据本发明，改进的导电纳米结构组件包括设置在导电衬底上的金属化纳米结构阵列。 衬底也可以金属化。 这样的组件提供从衬底到纳米结构的尖端的连续的电子传输。 与使用组件的几个装置一起描述制造这种组件的几种方式。