公开(公告)号：US4994887A

公开(公告)日：1991-02-19

申请号：US120558

申请日：1987-11-13

申请人： Louis N. Hutter ,  Mark E. Gibson ,  Jeffrey P. Smith ,  Shiu-Hang Yan ,  Arnold C. Conway ,  John P. Erdeljac ,  James D. Goon ,  AnhKim Duong ,  Mary A. Murphy ,  Susan S. Kearney

发明人： Louis N. Hutter ,  Mark E. Gibson ,  Jeffrey P. Smith ,  Shiu-Hang Yan ,  Arnold C. Conway ,  John P. Erdeljac ,  James D. Goon ,  AnhKim Duong ,  Mary A. Murphy ,  Susan S. Kearney

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L27/0623

摘要： An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.

摘要翻译： 描述了具有PMOS，NMOS和NPN晶体管的集成电路用于需要数字和模拟电路的应用。 该集成电路设计为允许在集成电路中使用标准CMOS单元，而无需重新设计。 提供了P +衬底（48），其上形成有第一P-外延层（46）。 分别为PMOS和NPN晶体管提供N + DUF区域（50,52）。 基部区域（68）通过注入和扩散形成在N阱（58）中。 在扩散之前，在基底（68）上形成氮化物层（70）以提供惰性退火。 基极扩散和集电极扩散发生在CMOS沟道停止和源极/漏极扩散之前，以防止改变MOS晶体管的扩散时间。

公开(公告)号：US06424005B1

公开(公告)日：2002-07-23

申请号：US09205657

申请日：1998-12-03

申请人： Chin-Yu Tsai ,  Taylor R. Efland ,  Sameer Pendharkar ,  John P. Erdeljac ,  Jozef Mitros ,  Jeffrey P. Smith ,  Louis N. Hutter

发明人： Chin-Yu Tsai ,  Taylor R. Efland ,  Sameer Pendharkar ,  John P. Erdeljac ,  Jozef Mitros ,  Jeffrey P. Smith ,  Louis N. Hutter

IPC分类号： H01L31113

CPC分类号： H01L29/66689 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816

摘要： An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.

摘要翻译： LDMOS器件（10,20,50,60）采用最小的特征尺寸制造方法制造，但克服了不对准Dwells的潜在问题（13）。 驻留（13）略微夸大，使得其n型掺杂剂被注入超过栅极区域（18）的源极边缘，这允许Dwell的n型区域在栅极区域（18）下扩散到足够的 距离消除不对准效应。

公开(公告)号：US06284669B1

公开(公告)日：2001-09-04

申请号：US09168194

申请日：1998-10-07

申请人： John P. Erdeljac ,  Louis N. Hutter ,  Jeffrey P. Smith ,  Han-Tzong Yuan ,  Jau-Yuann Yang ,  Taylor R. Efland ,  C. Matthew Thompson ,  John K. Arch ,  Mary Ann Murphy

发明人： John P. Erdeljac ,  Louis N. Hutter ,  Jeffrey P. Smith ,  Han-Tzong Yuan ,  Jau-Yuann Yang ,  Taylor R. Efland ,  C. Matthew Thompson ,  John K. Arch ,  Mary Ann Murphy

IPC分类号： H01L21302

CPC分类号： H01L29/66659 ,  H01L29/456 ,  H01L29/7835

摘要： A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).

摘要翻译： 公开了一种功率场效应晶体管，其包括分别设置在主体（40）和（42）的外表面上的铂硅化物接触层（74）和（78）的多晶硅栅极体（40）和（42）。 另外，该器件还包括在其外表面上形成有铂硅化物漏极接触层（76）和铂硅化物源极接触层（75）和（77）的n +漏极区域（64）。 在形成期间，侧壁间隔物（50）和（52）以及掩模体（70）和（72）用于确保与两个闸门体（40）和（42）间隔开的铂硅化物层（76）和 铂硅化物栅极接触层（74）和（78）。

公开(公告)号：US06153451A

公开(公告)日：2000-11-28

申请号：US2977

申请日：1998-01-05

申请人： Louis N. Hutter ,  John P. Erdeljac ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  John P. Erdeljac ,  Jeffrey P. Smith

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/366

CPC分类号： H01L29/7816 ,  H01L29/66689 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/456

摘要： A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.

摘要翻译： 一种在衬底的表面中增加形成在第二导电类型的第一导电区域的衬底上的晶体管的工作电压的方法。 然后在N阱区域中形成第一导电类型的N阱调节区域。 N阱调整区域延伸到N阱区域中的第一深度。 然后在N阱中形成第一导电类型的双扩散阱。 双扩散阱延伸到大于N阱调节区域的第一深度的第二深度，并且包含N阱的一部分。 然后在N阱中形成两个N-通道停止区。 两个N沟道停止区延伸到大于N阱调整区的深度的第三深度，并且包含N阱的一部分。

公开(公告)号：US5880002A

公开(公告)日：1999-03-09

申请号：US761293

申请日：1996-12-06

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L21/8249 ,  H01L21/331

CPC分类号： H01L21/8249 ,  Y10S148/01

摘要： A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36). Preferably, a CMOS structure (10) may be constructed elsewhere on the substrate concurrently with at least some of the steps for making the isolated vertical PNP transistor (11). For example, in one embodiment, the step of forming a P emitter region (40), an N base contact region (41), and a P collector contact region (44) are performed as a part of the simultaneous formation of source and drain regions (47 and 48) of the CMOS structure (10) elsewhere on the substrate (12). In another embodiment, the step of forming an N base contact (54) and a P collector contact (53) are performed as a part of a simultaneous formation of source and drain regions of a CMOS structure elsewhere on the substrate. In this embodiment, a separate deeper a P emitter region (52) is formed in the N well (19) to increase the emitter X.sub.J.

摘要翻译： 垂直PNP晶体管（11）及其制造方法包括在P基板（12）中形成N区域（19），并且在基板（12）中横向包围并部分地延伸到 N-区（19）。 在N-区域（19）的上方形成P区域（30），N区域（26）横向地被N +和N +区域（19和26）水平且垂直地与衬底隔离。 整体地形成半导体材料层（32），形成N阱（35）和周围的P阱（36），每个延伸到P区域（30）。 围绕P阱（36）形成隔离的N +阱（38），延伸到掩埋的N +区域（26）。 在N阱（35）的表面形成有P个发射极区域（40）和N个基极接触区域（41），在P阱（36）的表面形成有P个集电极接触区域（44）。 优选地，CMOS结构（10）可以与用于制造隔离的垂直PNP晶体管（11）的至少一些步骤同时在衬底上的其他地方构造。 例如，在一个实施例中，形成P发射极区域（40），N基极接触区域（41）和P集电极接触区域（44）的步骤被执行为同时形成源极和漏极 在衬底（12）上的其它地方的CMOS结构（10）的区域（47和48）。 在另一个实施例中，形成N基极触点（54）和P集电极触点（53）的步骤被执行为在基板的其他地方的CMOS结构的源极和漏极区域的同时形成的一部分。 在本实施例中，在N阱（19）中形成分开的较深的P发射极区（52）以增加发射极XJ。

公开(公告)号：US5929506A

公开(公告)日：1999-07-27

申请号：US937865

申请日：1997-09-25

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L29/00

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36). Preferably, a CMOS structure (10) may be constructed elsewhere on the substrate concurrently with at least some of the steps for making the isolated vertical PNP transistor (11). For example, in one embodiment, the step of forming a P emitter region (40), an N base contact region (41), and a P collector contact region (44) are performed as a part of the simultaneous formation of source and drain regions (47 and 48) of the CMOS structure (10) elsewhere on the substrate (12). In another embodiment, the step of forming an N base contact (54) and a P collector contact (53) are performed as a part of a simultaneous formation of source and drain regions of a CMOS structure elsewhere on the substrate. In this embodiment, a separate deeper a P emitter region (52) is formed in the N well (19) to increase the emitter X.sub.J.

摘要翻译： 垂直PNP晶体管（11）及其制造方法包括在P基板（12）中形成N区域（19），并且在基板（12）中横向包围并部分地延伸到 N-区（19）。 在N-区域（19）的上方形成P区域（30），N区域（26）横向地被N +和N +区域（19和26）水平且垂直地与衬底隔离。 整体地形成半导体材料层（32），形成N阱（35）和周围的P阱（36），每个延伸到P区域（30）。 围绕P阱（36）形成隔离的N +阱（38），延伸到掩埋的N +区域（26）。 在N阱（35）的表面形成有P个发射极区域（40）和N个基极接触区域（41），在P阱（36）的表面形成有P个集电极接触区域（44）。 优选地，CMOS结构（10）可以与用于制造隔离的垂直PNP晶体管（11）的至少一些步骤同时在衬底上的其他地方构造。 例如，在一个实施例中，形成P发射极区域（40），N基极接触区域（41）和P集电极接触区域（44）的步骤被执行为同时形成源极和漏极 在衬底（12）上的其它地方的CMOS结构（10）的区域（47和48）。 在另一个实施例中，形成N基极触点（54）和P集电极触点（53）的步骤被执行为在基板的其他地方的CMOS结构的源极和漏极区域的同时形成的一部分。 在本实施例中，在N阱（19）中形成分开的较深的P发射极区（52）以增加发射极XJ。

公开(公告)号：US5702959A

公开(公告)日：1997-12-30

申请号：US455945

申请日：1995-05-31

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L21/761 ,  H01L27/0623 ,  H01L29/7322 ,  Y10S148/03 ,  Y10S148/039 ,  Y10S148/109

摘要： A process for making a vertical PNP transistor and a transistor made by the process includes providing a highly doped semiconductor substrate (10) of P conductivity type. A first lightly doped P- layer (12) is epitaxially grown on the substrate (10). An N+ type buried layer impurity (18) is introduced into a surface region of the first lightly doped layer (12) that will underlie and define an island in which the vertical transistor will be constructed. A second lightly doped P- layer (16) is epitaxially grown on the first lightly doped layer (12) and the buried layer impurity (18). An N+ type isolation impurity is diffused into the second layer to form wells to laterally enclose an island (22) of the second layer (16) above the buried layer impurity (18). An N type base impurity (28) is diffused into the island (22) region of the second layer (16), and a P type emitter impurity (30) is diffused into the base region (28). A collector resistivity adjusting impurity (25) may optionally be diffused into the second layer (16) to reduce the collector resistance of the PNP transistor that is formed. Various steps in the construction of the vertical PNP transistor, such as diffusing the isolation impurity (18), diffusing the base impurity (28), and diffusing the emitter impurity (30), may be performed simultaneously with corresponding steps of a BiCMOS process.

摘要翻译： 用于制造垂直PNP晶体管和由该工艺制造的晶体管的工艺包括提供P导电型的高掺杂半导体衬底（10）。 在衬底（10）上外延生长第一轻掺杂P层（12）。 将N +型掩埋层杂质（18）引入到第一轻掺杂层（12）的表面区域中，该第一轻掺杂层将构成将构成垂直晶体管的基底并形成一个岛。 在第一轻掺杂层（12）和掩埋层杂质（18）上外延生长第二轻掺杂P层（16）。 N +型隔离杂质扩散到第二层中以形成阱以横向封闭第二层（16）上的掩埋层杂质（18）上方的岛（22）。 N型基极杂质（28）扩散到第二层（16）的岛（22）区域中，P型发射极杂质（30）扩散到基极区（28）中。 集电极电阻率调整杂质（25）可以任选地扩散到第二层（16）中，以减小形成的PNP晶体管的集电极电阻。 可以与BiCMOS工艺的相应步骤同时进行垂直PNP晶体管的构造中的各种步骤，例如扩散隔离杂质（18），扩散基极杂质（28）和扩散发射极杂质（30）。

公开(公告)号：US5472887A

公开(公告)日：1995-12-05

申请号：US149581

申请日：1993-11-09

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/0688 ,  H01L27/088 ,  H01L27/105

摘要： A semiconductor device (76) is provided with a high-voltage portion including NMOS transistor (78) and PMOS transistor (82b) and a low-voltage portion including NMOS transistor (80) and PMOS transistor 82(a). The high-voltage NMOS transistor (78) includes source/drain regions (90a, 90b) having N- regions (90a.sub.1, 90b.sub.1) that are self-aligned with a gate (78) and N+ regions (90a.sub.2, 90b.sub.2) that are self-aligned with sidewall spacers (91) formed on sidewalls of the gate (78) to improve reliability under continuous high voltage operating conditions. The low voltage NMOS transistor includes source/drain regions (92a, 92b) that are self-aligned with sidewall spacers (92) to permit channel lengths to be scaled to less than 2 microns. The low-voltage PMOS transistor (82a) and high-voltage PMOS transistor (82b) include source/drain regions (116a-116d) that are self-aligned with sidewall spacer extension regions (110a) formed over sidewall spacers (91) permitting low-voltage PMOS transistor channel lengths to be scaled to less than 2 microns.

摘要翻译： 半导体器件（76）设置有包括NMOS晶体管（78）和PMOS晶体管（82b）的高压部分和包括NMOS晶体管（80）和PMOS晶体管82（a）的低电压部分。 高压NMOS晶体管（78）包括具有与栅极（78）自对准的N区（90a1,90b1）和自我对准的N +区（90a2,90b2）的源/漏区（90a，90b） 与形成在栅极（78）的侧壁上的侧壁间隔物（91）对准，以提高连续高压操作条件下的可靠性。 低电压NMOS晶体管包括与侧壁间隔物（92）自对准的源极/漏极区域（92a，92b），以允许将沟道长度缩放到小于2微米。 低压PMOS晶体管（82a）和高电压PMOS晶体管（82b）包括源极/漏极区域（116a-116d），其与在侧壁间隔物（91）上形成的侧壁间隔物延伸区域（110a）自对准，允许低 电压PMOS晶体管沟道长度要缩放到小于2微米。

公开(公告)号：US06396109B1

公开(公告)日：2002-05-28

申请号：US09388943

申请日：1999-09-02

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L2976

CPC分类号： H01L21/8249

摘要： A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N− conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12). More particularly, the steps of forming the P conductivity type buried layer (30) may be performed a part of a simultaneous formation of a collector element of the PNP transistor (11) elsewhere on the substrate (12).

摘要翻译： 在BiCMOS工艺中制造隔离NMOS晶体管（10）的方法包括在P导电型半导体衬底（12）中形成N-导电型DUF层（19），随后形成交替的连续N +和P导电型掩埋区 （30,26）在衬底（12）中。 然后在衬底（12）上形成基本上本征的半导体材料层（32），其中分别在其上形成交替和连续的N和P导电类型阱（35,36）并延伸到N +和P导电类型埋置 地区（30,26）。 最后，NMOS源极和漏极区（48）形成在至少一个P导电型阱（35）中。 该方法优选与衬底（12）上的其它地方的双极晶体管结构（11）的构造同时进行。 更具体地，形成P导电型掩埋层（30）的步骤可以在衬底（12）上同时形成PNP晶体管（11）的集电极元件的其他部分的一部分。

公开(公告)号：US6033946A

公开(公告)日：2000-03-07

申请号：US761267

申请日：1996-12-06

申请人： Louis N. Hutter ,  Jeffrey P. Smith

发明人： Louis N. Hutter ,  Jeffrey P. Smith

IPC分类号： H01L21/8249 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/1087 ,  H01L21/8249 ,  H01L29/1083 ,  H01L29/78

摘要： A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12). More particularly, the steps of forming the P conductivity type buried layer (30) may be performed a part of a simultaneous formation of a collector element of the PNP transistor (11) elsewhere on the substrate (12).

摘要翻译： 在BiCMOS工艺中制造隔离NMOS晶体管（10）的方法包括在P导电型半导体衬底（12）中形成N-导电型DUF层（19），随后形成交替的连续N +和P导电型掩埋区 （30,26）在衬底（12）中。 然后在衬底（12）上形成基本上本征半导体材料层（32），其中分别在其上形成交替和连续的N和P导电类型阱（35,36）并且延伸到N +和P导电类型埋置 地区（30,26）。 最后，NMOS源极和漏极区（48）形成在至少一个P导电型阱（35）中。 该方法优选与衬底（12）上的其它地方的双极晶体管结构（11）的构造同时进行。 更具体地，形成P导电型掩埋层（30）的步骤可以在衬底（12）上同时形成PNP晶体管（11）的集电极元件的其他部分的一部分。