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    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    1.
    发明申请
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US20050106897A1

    公开(公告)日：2005-05-19

    申请号：US10832952

    申请日：2004-04-27

    申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8234 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3144

    摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    3.
    发明授权
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US07190024B2

    公开(公告)日：2007-03-13

    申请号：US11329217

    申请日：2006-01-10

    申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L21/0214 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/7881

    摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    5.
    发明授权
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US07041557B2

    公开(公告)日：2006-05-09

    申请号：US10832952

    申请日：2004-04-27

    申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC分类号： H01L21/366

    CPC分类号： H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3144

    摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。

    Non-volatile memory device and method of manufacturing the same
    7.
    发明申请
    Non-volatile memory device and method of manufacturing the same 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20060170034A1

    公开(公告)日：2006-08-03

    申请号：US11339741

    申请日：2006-01-25

    申请人： Sung-Woo Park ,  Sung-Taeg Kang ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Ji-Hoon Park

    发明人： Sung-Woo Park ,  Sung-Taeg Kang ,  Seung-Beom Yoon ,  Yong-Tae Kim ,  Ji-Hoon Park

    IPC分类号： H01L29/792

    CPC分类号： H01L29/66833 ,  H01L29/40117 ,  H01L29/792

    摘要： Provided are a non-volatile memory device having an improved electric characteristic and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a substrate having a sloped portion formed therein, a first gate electrode pattern having a stacked structure in which an electric charge tunneling layer pattern, an electric charge trapping layer pattern, an electric charge shielding layer pattern, and a storage gate electrode pattern are conformably stacked on the sloped portion, a gate insulating layer pattern extending from a side of the first gate electrode pattern to the substrate, a second gate electrode pattern formed on the gate insulating layer pattern, a first junction region arranged at a side wall of the first gate electrode pattern, which does not face the second gate electrode pattern, and formed in the substrate, and a second junction region arranged at a side wall of the second gate electrode pattern, which does not face the first gate electrode pattern, and formed in the substrate.

    摘要翻译： 提供了具有改进的电特性的非易失性存储器件和制造非易失性存储器件的方法，其中非易失性存储器件包括其中形成有倾斜部分的衬底，第一栅电极图案具有堆叠 其中电荷隧道层图案，电荷捕获层图案，电荷屏蔽层图案和存储栅极电极图案顺应地堆叠在倾斜部分上的结构，从第一部分的侧面延伸的栅极绝缘层图案 栅电极图案到基板，形成在栅极绝缘层图案上的第二栅极电极图案，布置在第一栅电极图案的侧壁处的第一接合区域，其不面向第二栅电极图案，并形成在第 衬底和布置在第二栅电极图案的侧壁处的第二接合区域，其不面向顶部 t栅电极图案，并形成在基板中。

    EEPROM device and manufacturing method thereof
    8.
    发明申请
    EEPROM device and manufacturing method thereof 失效
    EEPROM装置及其制造方法

    公开(公告)号：US20060006452A1

    公开(公告)日：2006-01-12

    申请号：US11087127

    申请日：2005-03-23

    申请人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    发明人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

    摘要翻译： 提供了一种EEPROM器件及其制造方法。 EEPROM装置由包括存储晶体管和位于半导体衬底上的串联选择晶体管的一个单元组成，并且包括位于存储晶体管的侧面区域上的源极区域，位于选择区域的一个侧面区域的漏极区域 面对源极区域的晶体管，以及形成在存储晶体管和选择晶体管之间的浮置结区，其中浮置结区域包括在存储晶体管占据的区域下朝向源极区域延伸的第一掺杂区域和掺杂 其具有与第一掺杂区域相对的导电掺杂剂并且形成为围绕第一掺杂区域。

    EEPROM device having first and second doped regions that increase an effective channel length
    9.
    发明授权
    EEPROM device having first and second doped regions that increase an effective channel length 失效
    具有增加有效沟道长度的第一和第二掺杂区的EEPROM器件

    公开(公告)号：US07408230B2

    公开(公告)日：2008-08-05

    申请号：US11087127

    申请日：2005-03-23

    申请人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    发明人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

    摘要翻译： 提供了一种EEPROM器件及其制造方法。 EEPROM装置由包括存储晶体管和位于半导体衬底上的串联选择晶体管的一个单元组成，并且包括位于存储晶体管的侧面区域上的源极区域，位于选择区域的一个侧面区域的漏极区域 面对源极区域的晶体管，以及形成在存储晶体管和选择晶体管之间的浮置结区，其中浮置结区域包括在存储晶体管占据的区域下朝向源极区域延伸的第一掺杂区域和掺杂 其具有与第一掺杂区域相对的导电掺杂剂并且形成为围绕第一掺杂区域。

    Eeprom and methods of fabricating the same
    10.
    发明申请
    Eeprom and methods of fabricating the same 审中-公开
    Eeprom及其制造方法

    公开(公告)号：US20070018230A1

    公开(公告)日：2007-01-25

    申请号：US11490768

    申请日：2006-07-21

    申请人： Weon-Ho Park ,  Byoung-Ho Kim ,  Sang-Woo Kang ,  Jeong-Uk Han ,  Sung-Woo Park

    发明人： Weon-Ho Park ,  Byoung-Ho Kim ,  Sang-Woo Kang ,  Jeong-Uk Han ,  Sung-Woo Park

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66825

    摘要： An EEPROM includes a tunneling opening having an inclined or a stepped sidewall. A tunnel insulation layer is formed within the tunneling opening. Using a flowed photoresist pattern as an etching mask, the gate insulator is etched to form a tunneling opening having an inclined sidewall. Thus, the tunnel insulation layer can be formed in a smaller area than an area defined by a photolithography. As a result, a width of an active region and a width of a wordline are decreased to reduce a unit cell size.

    摘要翻译： EEPROM包括具有倾斜或阶梯状侧壁的隧道开口。 在隧道开口内形成隧道绝缘层。 使用流动的光致抗蚀剂图案作为蚀刻掩模，蚀刻栅极绝缘体以形成具有倾斜侧壁的隧道开口。 因此，隧道绝缘层可以形成在比由光刻限定的区域更小的区域中。 结果，有效区域的宽度和字线的宽度减小以减小单元电池尺寸。