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    Interconnect structure and method of fabrication of same
    2.
    发明授权
    Interconnect structure and method of fabrication of same 失效
    互连结构及其制造方法

    公开(公告)号：US07335588B2

    公开(公告)日：2008-02-26

    申请号：US11107074

    申请日：2005-04-15

    申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

    发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Meeyoung H. Yoon

    IPC分类号： H01L24/4763

    CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

    摘要翻译： 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

    Sidewall spacer structure for self-aligned contact and method for forming the same
    4.
    发明授权
    Sidewall spacer structure for self-aligned contact and method for forming the same 有权
    用于自对准接触的侧壁间隔结构及其形成方法

    公开(公告)号：US07056828B2

    公开(公告)日：2006-06-06

    申请号：US10404951

    申请日：2003-03-31

    申请人： Tae-Young Chung ,  Jae-Goo Lee ,  Dong-Jun Lee

    发明人： Tae-Young Chung ,  Jae-Goo Lee ,  Dong-Jun Lee

    IPC分类号： H01L24/4763

    CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76837

    摘要： In one embodiment, adjacent conductive patterns are formed overlying a semiconductor substrate. The conductive patterns each have a conductive line and a capping layer. A first spacer formation layer is formed between the adjacent conductive patterns. The first spacer formation layer is formed between the top surface of the capping layer and the bottom surface of the conductive line. A conformal second spacer formation layer is formed on the conductive patterns. A first interlayer insulating layer is formed on the conformal second spacer formation layer. Next, an opening is formed to extend to a portion of the first spacer formation layer, in the first interlayer insulating layer. The portion of the first spacer formation layer is etched, using the second spacer formation layer as an etch mask, to form a single-layer spacer on sidewalls of the conductive patterns, concurrently with a contact hole.

    摘要翻译： 在一个实施例中，在半导体衬底上形成相邻的导电图案。 导电图案各自具有导电线和封盖层。 在相邻的导电图案之间形成第一间隔物形成层。 第一间隔物形成层形成在覆盖层的顶表面和导电线的底表面之间。 在导电图案上形成保形第二间隔物形成层。 在保形第二间隔物形成层上形成第一层间绝缘层。 接下来，形成在第一层间绝缘层中延伸到第一间隔物形成层的一部分的开口。 使用第二间隔物形成层作为蚀刻掩模蚀刻第一间隔物形成层的部分，以在接触孔同时在导电图案的侧壁上形成单层间隔物。