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公开(公告)号：US06424172B1
公开(公告)日：2002-07-23
申请号：US09796996
申请日：2001-02-28
IPC分类号： H03K19082
CPC分类号： H03H11/0422
摘要： This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor. Thus, a released “zero” can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
摘要翻译： 本发明涉及具有可编程零点的前馈类型的电路结构，特别是用于合成时间连续滤波器。 该结构包括互连至少一个互连节点并连接在第一单元的第一信号输入和第二单元的输出端之间的一对放大单元，每个单元包括一对具有共同的导通端子并具有 其它导电端子通过相应的偏置构件分别耦合到第一电压基准。 所述结构还包括将所述第一单元的节点连接到所述输出端子并且包括具有连接到所述第一单元的节点的控制端子的晶体管，连接到所述输出端子的第一导通端子和第二导通 端子通过电容器耦合到第二参考电压。 因此，可以在极零复平面的右半平面中引入释放的“零”，以改善组增益的平坦化。
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2.发明授权Variable-gain multistage amplifier with broad bandwidth and reduced phase variations 有权可变增益多级放大器，带宽宽，相位变化减小公开(公告)号：US06246289B1
公开(公告)日：2001-06-12
申请号：US09507562
申请日：2000-02-18
IPC分类号： H03F345
CPC分类号： H03G1/0023
摘要： A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors. The amplifier further includes two circuit branches, each of which is constituted by a bipolar transistor and by a third current source, which is respectively connected to the collector terminal and emitter terminal of the bipolar transistor, in which the base terminal receives the differential voltage signal and the collector terminal is connected to the cathode terminal of a respective one of the two diodes, the circuit branches being mutually connected by means of a pair of capacitors.
摘要翻译： 一种具有宽带宽和相位变化较小的可编程增益多级放大器，具有由第一电流源偏置的差分输入级，馈送差分电压信号，该级连接到阴极端子连接的一对二极管 到由双极晶体管的集电极端子提供的由第二电流源偏置并且其中集电极端子连接到负载电阻器的各个双极晶体管，放大器的差分输出被提供。 放大器还包括两个电路分支，每个电路分支由双极晶体管和第三电流源构成，第三电流源分别连接到双极晶体管的集电极端子和发射极端子，其中基极端子接收差分电压信号 并且集电极端子连接到两个二极管中的相应一个的阴极端子，电路分支通过一对电容器相互连接。
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3.发明授权Amplifier with programmable gain and input linearity usable in high-frequency lines 有权具有可编程增益和输入线性度的放大器可用于高频线路
公开(公告)号：US6037838A
公开(公告)日：2000-03-14
申请号：US264296
申请日：1999-03-08
CPC分类号： H03G7/06 , H03G1/0023
摘要： An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.
摘要翻译： 在高频下具有可编程增益和输入线性度的放大器可以增加增益，而不会影响输入线性度并且不会显着增加电流消耗。 放大器包括输入级，其接收用于通过压缩执行其电流转换的电压信号。 输出级连接到输入级，并且解压缩由输入级提供的信号，以产生其增益放大。 放大器还包括插入在输入级和输出级之间的至少一个电流放大器级。 至少一个电流放大器包括串联连接到负载二极管和电流源的至少一个双极晶体管。 在所述至少一个放大器级中提供所述负载二极管的跨导的减小以确定所述放大器的可编程增益因子。
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4.发明授权
公开(公告)号：US6133771A
公开(公告)日：2000-10-17
申请号：US263757
申请日：1999-03-05
CPC分类号： H03K7/08
摘要： A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.
摘要翻译： 器件产生具有可编程持续时间的高精度脉冲。 该装置包括第一，第二和第三脉冲发生器电路。 第一脉冲发生器电路在输入端接收脉冲产生指令信号，并在输出端提供用于将寄存器的内容装入计数器的第一脉冲。 第二脉冲发生器电路由第一脉冲发生器电路提供的第一脉冲触发。 第三脉冲发生器电路由第二脉冲发生器电路提供的第二脉冲触发，并产生第三脉冲以重新启动第二脉冲发生器电路。 由第二脉冲发生器电路提供的第二脉冲为计数器形成时钟信号以产生计数器的减量。 来自计数器的输出信号是要产生的脉冲信号。 脉冲信号的持续时间由计数器的内容决定。
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5.发明授权Feedforward circuit structure with programmable zeros for providing programmable group delay of a wide signal band 有权具有可编程零点的前馈电路结构，用于提供宽信号频带的可编程组延迟
公开(公告)号：US6127873A
公开(公告)日：2000-10-03
申请号：US221199
申请日：1998-12-23
CPC分类号： H03H11/04
摘要： A feedforward circuit structure with programmable zeros for synthesizing continuous-time filters, delay lines, and the like is described. The circuit comprises a first cell and a second cell which are cascade-connected. Each one of the first and second cells comprises first and second pairs of bipolar transistors. The emitter terminals of the first pair of transistors are connected to a first current source, and the emitter terminals of the second pair of transistors are connected to a second current source. A first high-impedance element is connected between the first and second pairs of transistors, and a second high-impedance element is connected at an output of the second pair of transistors. A fifth transistor is connected between the collector terminal of a first transistor of the first pair of transistors and the collector terminal of a second transistor of the second pair of transistors. The base terminal of the fifth transistor receives a signal which is taken from the collector terminal of the first transistor of the first pair of transistors, with the signal being taken with a positive sign in the first cell and with a negative sign in the second cell, in order to determine a transfer function with a pair of singularities at the numerator. The second transistors of the first and second pairs of transistors are controlled respectively by third and fourth current sources which have mutually different values.
摘要翻译： 描述了具有用于合成连续时间滤波器，延迟线等的可编程零的前馈电路结构。 电路包括级联的第一单元和第二单元。 第一和第二单元中的每一个包括第一和第二对双极晶体管。 第一对晶体管的发射极端子连接到第一电流源，第二对晶体管的发射极端子连接到第二电流源。 第一高阻抗元件连接在第一和第二对晶体管之间，第二高阻抗元件连接在第二对晶体管的输出端。 第五晶体管连接在第一对晶体管的第一晶体管的集电极端子与第二对晶体管的第二晶体管的集电极端子之间。 第五晶体管的基极接收从第一晶体管的第一晶体管的集电极端子取出的信号，信号以第一单元中的正号取，第二单元中具有负号 ，以便在分子处确定具有一对奇异点的传递函数。 第一和第二对晶体管的第二晶体管分别由具有相互不同的值的第三和第四电流源控制。
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公开(公告)号：US5495166A
公开(公告)日：1996-02-27
申请号：US45465
申请日：1993-04-08
CPC分类号： G05F3/24 , H03K17/145
摘要： A threshold voltage generator for a field-effect transistor, being of a type adapted to compensate for variations of the threshold voltage from a nominal value, comprising a first amplifier having a first input connected to a current generator; a second amplifier connected ahead of a second input of the first amplifier and having an input connected to another current generator; and a third amplifier connected after the first amplifier and having an output adapted to produce the value of said threshold voltage.
摘要翻译： 一种用于场效应晶体管的阈值电压发生器，其类型适于补偿阈值电压与标称值的变化，包括具有连接到电流发生器的第一输入的第一放大器; 连接在第一放大器的第二输入端的第二放大器，并具有连接到另一电流发生器的输入端; 以及连接在所述第一放大器之后并具有适于产生所述阈值电压值的输出端的第三放大器。
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公开(公告)号：US06667868B2
公开(公告)日：2003-12-23
申请号：US09970540
申请日：2001-10-03
IPC分类号： H02H504
CPC分类号： H02H5/041
摘要： A multi-channel power shut-down circuit that includes a plurality of channel disabler circuits formed on a common substrate where each of the channel disabler circuits includes a first combinational logic and a second combinational logic having an input coupled to an output of the first combinational logic and having a channel disable output, and a channel overcurrent detector coupled to an input of the first combinational logic. A thermal warning detector is also formed on the common substrate and coupled to the inputs of the first combinational logic of the plurality of channel disabler circuits. A thermal shutdown detector formed on the common substrate and coupled to the inputs of the second combinational logic of the plurality of channel disabler circuits.
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8.发明授权公开(公告)号：US06222751B1
公开(公告)日：2001-04-24
申请号：US09571354
申请日：2000-05-15
申请人： Salvatore Portaluri , Alessandro Savo , Maurizio Nessi , Luigi Eugenio Garbelli , Giorgio Sciacca
发明人： Salvatore Portaluri , Alessandro Savo , Maurizio Nessi , Luigi Eugenio Garbelli , Giorgio Sciacca
IPC分类号： H02M75387
CPC分类号： H03K17/166 , H02M7/53803
摘要： A driver circuit includes a half-bridge output stage including two transistors with a common terminal for connection as the driver output to a coil of a DC motor. Two amplifiers drive the transistors in the push-pull operation and two capacitors are connected between the driver output and one input of a respective amplifier to form feedback loops for controlling the output slew-rate. Two current generators are selectively connected to an input of either of the amplifiers through respective pairs of switches. A commutation sequencer turns on and off the switches according to a commutation program. Comparators are connected to the drive output for detecting predetermined output voltage conditions and providing the commutation sequencer with signals for conditioning the commutation program as a function of the detected voltage conditions.
摘要翻译： 驱动器电路包括半桥输出级，其包括具有用于连接的公共端子的两个晶体管，因为驱动器输出到直流电动机的线圈。 两个放大器在推挽操作中驱动晶体管，并且两个电容器连接在驱动器输出和相应放大器的一个输入端之间，以形成用于控制输出转换速率的反馈回路。 两个电流发生器通过相应的开关对选择性地连接到任一放大器的输入。 换向顺序器根据换向程序打开和关闭开关。 比较器连接到驱动输出端，用于检测预定的输出电压状况，并根据检测到的电压条件向换向定序器提供用于调节换向程序的信号。
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9.发明授权Method and circuit of soft start and of power monitor for IC with multiple supplies 有权具有多种电源的IC软启动和功率监控的方法和电路公开(公告)号：US06320439B1
公开(公告)日：2001-11-20
申请号：US09657436
申请日：2000-09-07
IPC分类号： H03K302
摘要： The monitoring of multiple supply voltages of an integrated circuit is done using a single external capacitor connected to a pin of the integrated circuit. Part of the multiple supply voltages are externally generated and part are internally generated. The internally generated supply voltages may include different voltages with different signs. A logic signal indicating that all the supply voltages have reached pre-established values before enabling functioning of the integrated circuit is generated after an initial soft start phase of the turn-on process.
摘要翻译： 使用连接到集成电路引脚的单个外部电容器对集成电路的多个电源电压进行监控。 多个电源电压的一部分是外部产生的，部分内部产生。 内部产生的电源电压可以包括具有不同符号的不同电压。 指示在使能功能的集成电路之前所有电源电压达到预定值的逻辑信号在开启过程的初始软启动阶段之后产生。
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公开(公告)号：US5654675A
公开(公告)日：1997-08-05
申请号：US611831
申请日：1996-03-06
CPC分类号： H03L7/0891 , H03L7/099 , H03L7/107 , H03L2207/04 , H03L7/0995
摘要： A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.
摘要翻译： 具有改进的抖动特性的完全集成的锁相环（PLL）使用相同的数/模转换器（DAC），其通常用于控制低通环路滤波器的时间常数，以控制连接在输出端 压控振荡器和地的电压 - 电流转换输入级。 电容在循环传递函数中引入了第三极点。 以这种方式，传递函数的零和第三极之间的频域分离保持不变; 因此，阻尼因子保持恒定，同时PLL的ω0变化。
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