公开(公告)号：US06739040B1

公开(公告)日：2004-05-25

申请号：US09696179

申请日：2000-10-26

申请人： Shigeo Nakamura ,  Tadahiko Yokota

发明人： Shigeo Nakamura ,  Tadahiko Yokota

IPC分类号： H05K636

CPC分类号： H05K3/4069 ,  H05K3/0035 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/381 ,  H05K3/426 ,  H05K3/4661 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/066 ,  H05K2203/068 ,  H05K2203/085 ,  H05K2203/1383 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

摘要： The present invention relates to a method of manufacturing a multilayered printed wiring board by a buildup system in which a conductive circuit layer and an insulating layer are alternately piled up. This method also involves using an adhesive film to facilitate manufacturing the multilayered printed wiring board having excellent surface smoothness at satisfactory yields.

摘要翻译： 本发明涉及一种通过积层系统制造多层印刷线路板的方法，其中导电电路层和绝缘层交替堆叠。 该方法还涉及使用粘合膜以便于以令人满意的产率制造具有优异表面平滑度的多层印刷线路板。