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公开(公告)号：US12052021B2
公开(公告)日：2024-07-30
申请号：US17931165
申请日：2022-09-12
CPC分类号： H03L7/0891 , H03L7/087 , H03L7/095
摘要： A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.
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公开(公告)号：US20240154615A1
公开(公告)日：2024-05-09
申请号：US18414273
申请日：2024-01-16
发明人： WeiShuo Lin
CPC分类号： H03L7/07 , H03L7/0816 , H03L7/095
摘要： A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.
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公开(公告)号：US20240085973A1
公开(公告)日：2024-03-14
申请号：US18514807
申请日：2023-11-20
申请人： Intel Corporation
CPC分类号： G06F1/3296 , G01R19/2513 , H03K5/24 , H03K19/20 , H03L7/093 , H03L7/095
摘要： An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
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公开(公告)号：US20240039543A1
公开(公告)日：2024-02-01
申请号：US18256059
申请日：2020-12-14
CPC分类号： H03L7/095 , H03L7/087 , H03L2207/50
摘要： An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension. The apparatus also comprises a comparator configured to provide the indication of the phase difference based on the digital pulse length representations provided by the first and second TDCs. Corresponding digital phase-locked loop (DPLL) and communication device are also disclosed.
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公开(公告)号：US11664808B2
公开(公告)日：2023-05-30
申请号：US17955615
申请日：2022-09-29
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/095
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
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公开(公告)号：US11588488B1
公开(公告)日：2023-02-21
申请号：US17546662
申请日：2021-12-09
申请人： Raytheon Company
发明人： Gary Ian Moore
摘要： A dual-loop phase-locking circuit combines a conventional phase-frequency-detector (PFD) and frequency-divider based first loop to lock an output signal frequency to a multiple of a reference signal frequency within a first loop bandwidth BW1 with a second loop to simultaneously lock the output signal phase to a second signal independently locked to the same multiple of the reference signal. The second loop integrates the phase error between the output signal and the second signal, and applies an offset at the PFD output in the first loop to reduce the first loop phase errors within a second loop bandwidth BW2 (
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公开(公告)号：US11539369B2
公开(公告)日：2022-12-27
申请号：US17538825
申请日：2021-11-30
发明人： WeiShuo Lin
摘要： A duty-cycle corrector circuit produces a clock signal with a given duty cycle (e.g., fifty percent) or with a substantially given duty cycle. The DC corrector circuit includes a delay-locked loop (DLL) circuit and a duty-cycle correction (DCC) circuit. The DLL circuit is operable to adjust a delay between local clock signals until the phase difference between the local clock signals equals or is substantially equal to zero. The DCC circuit is operable to adjust the duty cycles of the local clock signals until the duty-cycle error equals or is substantially equal to zero. The duty-cycle error equals or substantially equals zero when the duty cycles of the local clock signals equal or are substantially equal to fifty percent.
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公开(公告)号：US20220360258A1
公开(公告)日：2022-11-10
申请号：US17538291
申请日：2021-11-30
发明人： Wei Shuo Lin
摘要： One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.
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公开(公告)号：US11489530B2
公开(公告)日：2022-11-01
申请号：US17531927
申请日：2021-11-22
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
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公开(公告)号：US11387815B2
公开(公告)日：2022-07-12
申请号：US17119937
申请日：2020-12-11
申请人： Intel Corporation
发明人： William Li , Mohsen Nasroullahi , Khoa Nguyen
IPC分类号： H03K3/03 , H03K5/131 , H03K5/133 , H03L7/081 , H03L7/087 , H03L7/095 , H03L7/099 , H03L7/197
摘要： An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency monitor coupled to the ring oscillator to monitor frequency at an output of at least two delay stages of the ring oscillator.
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