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公开(公告)号：US12052028B2
公开(公告)日：2024-07-30
申请号：US17844413
申请日：2022-06-20
申请人： SILEAD Inc.
发明人： Jinling Zhou
CPC分类号： H03M1/462 , H03K19/1774 , H03K19/20 , H03M1/206 , H03M1/361
摘要： A SAR ADC and an electronic device are disclosed. The SAR ADC includes a read clock generation circuit, configured to connect to a first output terminal and a second output terminal of a dynamic comparator, and generate a read clock signal for reading a first or a second comparison result based on the first and the second comparison result received from the dynamic comparator. The invention reads the comparison result using the read clock signal generated by grabbing the output of the comparator, and can improve the overall analog-to-digital conversion speed of the SAR ADC. Further, the present invention can detect the occurrence of metastable state of the comparator by judging that the output of the comparator has no pulse, and read the comparison result based on the backup clock generated by the operating clock of the comparator.
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2.发明公开公开(公告)号：US20240235572A9
公开(公告)日：2024-07-11
申请号：US18490931
申请日：2023-10-20
发明人： Arindam SANYAL
CPC分类号： H03M1/462 , H03M1/0668 , H03M1/201
摘要： A low-pass and band-pass delta-sigma (ΔΣ) analog-to-digital converter (ADC) device for sensor interface is disclosed. The device includes a first stage comprising a low-resolution passive integrator-based noise-shaping successive approximation register (SAR) ADC and a second stage comprising a voltage-controlled oscillator (VCO)-ADC.
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3.发明公开公开(公告)号：US20230198540A1
公开(公告)日：2023-06-22
申请号：US17555270
申请日：2021-12-17
IPC分类号： H03M1/20
CPC分类号： H03M1/201
摘要： Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.
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公开(公告)号：US11664814B2
公开(公告)日：2023-05-30
申请号：US17461400
申请日：2021-08-30
CPC分类号： H03M1/203 , G06G7/30 , H03F3/45183 , H03M1/365
摘要： Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.
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公开(公告)号：US11652491B2
公开(公告)日：2023-05-16
申请号：US17390852
申请日：2021-07-30
CPC分类号： H03M1/0641
摘要： Mechanisms for reducing or eliminating a quantization error caused by a quantizer of a continuous-time (CT) residue generation system are disclosed. In particular, systems and methods described herein are based on using a dither generation and injection circuit that can perform a high-pass filtering of the additive dither signal (i.e., a high-pass shaped dither signal). Using high-pass shaped dither signals is expected to improve quantizer linearity without significantly reducing the available error correction range. The applied dither may be particularly effective at minimizing signal-dependent distortion in ADC output spectrum caused by the quantizer when the quantization error cancellation accuracy may be insufficient.
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6.发明申请公开(公告)号：US20220224350A1
公开(公告)日：2022-07-14
申请号：US17614336
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , Chongqing GigaChip Technology Co., Ltd.
发明人： Tao LIU , Jian'an WANG , Yuxin WANG , Shengdong HU , Zhou YU , Minming DENG , Daiguo XU , Lu LIU , Dongbing FU , Jun LUO , Xu WANG , Yan WANG , Zicheng XU
摘要： A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.
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公开(公告)号：US11196441B2
公开(公告)日：2021-12-07
申请号：US15979562
申请日：2018-05-15
发明人： Yasuhide Takase , Yasuyuki Matsuya
摘要： A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a Δ modulation on the analog input signal which is converted into a digital signal.
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公开(公告)号：US11159169B2
公开(公告)日：2021-10-26
申请号：US16877118
申请日：2020-05-18
申请人： Analog Devices, Inc.
摘要： Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.
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公开(公告)号：US20210305994A1
公开(公告)日：2021-09-30
申请号：US17011115
申请日：2020-09-03
发明人： Kyoungho KIM , Dongryeol OH , Seungtak RYU
IPC分类号： H03M1/20 , H03M1/12 , G11C7/16 , G11C11/408
摘要： An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n−1)th differential signal pairs among n differential signal pairs, in response to each of the n first differential node pairs being sequentially charged, sequentially generate each of n first differential data pairs, and sequentially generate each of n upper differential data pairs to be used as n-bit upper digital data, in response to a respective one of the sequentially-generated n first differential data pairs. The first analog-digital conversion unit is further configured to, during a second analog-digital conversion operation, simultaneously discharge each of the n first differential node pairs, in response to a nth differential signal pair among the n differential signal pairs.
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10.发明授权公开(公告)号：US11128311B1
公开(公告)日：2021-09-21
申请号：US17016574
申请日：2020-09-10
发明人： Ming-Hung Chang , Jui-Chu Chung
摘要： An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.
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