公开(公告)号：WO2009079752A8

公开(公告)日：2010-01-14

申请号：PCT/CA2008002180

申请日：2008-12-11

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI

Inventor： KIM JIN-KI

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

公开(公告)号：WO2010000062A1

公开(公告)日：2010-01-07

申请号：PCT/CA2009/000892

申请日：2009-06-30

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki ,  PETRIE, William

Inventor： KIM, Jin-Ki ,  PETRIE, William

IPC: G11C16/02 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M-1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract translation: 一种多位单元（MBC）非易失性存储装置，方法和系统，其中用于向/从存储器阵列写入/读取数据的控制器通过选择性地反转数据字来控制数据的极性，以使位的数量最大化为 （M-1）个虚拟页面内编程，并选择性地反转数据字以最小化要在第M个虚拟页面中编程的位数，其中M是每个单元的位数。 当数据字反转时，设置相应的极性控制标志。 当从M个虚拟页面读取时，根据相应的极性标志选择性地反转数据。 一些最高阈值电压编程状态在减少。 这提供了编程单元阈值电压的更严格的分配，降低的功耗，减少的编程时间和增强的器件可靠性。

公开(公告)号：WO2009097681A1

公开(公告)日：2009-08-13

申请号：PCT/CA2009000130

申请日：2009-02-03

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI

Inventor： KIM JIN-KI

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08

CPC classification number: G11C16/08 ,  G06F12/0246 ,  G11C7/1045 ,  G11C8/08 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/22

Abstract: A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank.

Abstract translation: 具有至少两个存储体的闪速存储器件，其中每个存储体具有可独立配置的页面大小和核心控制器。 核心控制器是每个银行本地的，并且管理银行的存储器访问操作，包括读取，编程和擦除操作。 每个核心控制器控制行电路，列电路，电压发生器和本地输入/输出路径电路的定时和激活，用于存储体的相应存储器存取操作。 并发操作可在多个银行中执行，以提高性能。 每个银行的页面大小可配置页面大小的配置数据，以便仅响应于地址数据激活所选择的字线。 在上电时，可以将组态数据加载到存储设备中，以进行存储体的静态页面配置，或者可以通过每个命令接收配置数据以允许存储体的动态页面配置。

公开(公告)号：WO2009092152A8

公开(公告)日：2009-07-30

申请号：PCT/CA2008/002155

申请日：2008-12-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

Inventor： KIM, Jin-Ki

IPC: G11C16/06

Abstract: Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and each of the data paths accommodates that bit width.

公开(公告)号：WO2009086618A1

公开(公告)日：2009-07-16

申请号：PCT/CA2008/002287

申请日：2008-12-23

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

Inventor： KIM, Jin-Ki

IPC: G11C16/14 ,  G11C16/24

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

Abstract translation: 具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。 在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。 当井区的面积减小时，每个井区的电容相应减小。 因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器单元的较高速度的擦除。 或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。 降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

公开(公告)号：WO2009079752A1

公开(公告)日：2009-07-02

申请号：PCT/CA2008/002180

申请日：2008-12-11

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

Inventor： KIM, Jin-Ki

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

公开(公告)号：WO2008101317A1

公开(公告)日：2008-08-28

申请号：PCT/CA2008/000273

申请日：2008-02-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  PYEON, Hong, Beom ,  KIM, Jin-Ki ,  OH, HakJune

Inventor： PYEON, Hong, Beom ,  KIM, Jin-Ki ,  OH, HakJune

IPC: G11C7/24 ,  G11C19/00

CPC classification number: G06F13/4243 ,  G06F13/4247

Abstract: An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Abstract translation: 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：WO2008074140A1

公开(公告)日：2008-06-26

申请号：PCT/CA2007/002304

申请日：2007-12-18

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

Inventor： KIM, Jin-Ki

IPC: G11C7/10 ,  G06F12/00 ,  G06F13/14 ,  G11C11/4063 ,  G11C11/413 ,  G11C7/20

CPC classification number: G11C14/0018 ,  G11C11/005

Abstract: A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.

Abstract translation: 提供了用于存储数据的混合固态存储器系统。 固态存储器系统包括易失性固态存储器，非易失性固态存储器和存储器控制器。 此外，提供了一种用于将数据存储在固态存储器系统中的方法。 该方法包括以下步骤。 存储器控制器接收写命令。 响应于写命令，写数据存储在易失性存储器中。 响应于数据传输请求，数据从易失性存储器传送到非易失性存储器。

公开(公告)号：WO2008067658A1

公开(公告)日：2008-06-12

申请号：PCT/CA2007/002182

申请日：2007-12-04

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  OH, HakJune ,  PYEON, Hong Beom ,  KIM, Jin-Ki

Inventor： OH, HakJune ,  PYEON, Hong Beom ,  KIM, Jin-Ki

IPC: G11C8/18 ,  G06F12/00 ,  G11C11/34 ,  G11C16/02 ,  G11C8/04 ,  G11C8/06

CPC classification number: G11C16/08 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/20

Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

Abstract translation: 提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。 存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。 每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。 每个存储器命令特定于目标存储器件的存储器类型。 存储器命令和存储器响应的数据路径由互连提供。 给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。 在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。 存储器响应被传送到存储器控制器。

公开(公告)号：WO2008067642A1

公开(公告)日：2008-06-12

申请号：PCT/CA2007/002147

申请日：2007-11-29

Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  PYEON, Hong Beom ,  OH, HakJune ,  SUMI, Shuji ,  KIM, Jin-Ki

Inventor： PYEON, Hong Beom ,  OH, HakJune ,  SUMI, Shuji ,  KIM, Jin-Ki

IPC: G11C8/06 ,  G11C16/20 ,  G11C8/12

CPC classification number: G11C16/20 ,  G11C8/12

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (Sl) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a "don't care" code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。 每个设备都有其设备类型的设备类型信息。 包含在串行输入（S1）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 在将不同的设备类型分别提供给互连设备的情况下，在不同设备类型的每一种中生成顺序ID，并且还识别每种设备类型的总数。 在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异如何。