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    A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
    1.
    发明申请
    A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 审中-公开
    具有用于将离散存储器装置连接到系统的桥接装置的组合存储器

    公开(公告)号：WO2010043032A8

    公开(公告)日：2010-07-08

    申请号：PCT/CA2009001451

    申请日：2009-10-14

    Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI ,  PYEON HONG BEOM

    Inventor： KIM JIN-KI ,  PYEON HONG BEOM

    IPC: G11C7/10 ,  G11C5/06 ,  G11C7/22 ,  G11C16/06

    CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C5/025

    Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

    Abstract translation: 一种包括分立存储器装置和桥装置的复合存储器装置，用于响应于具有与存储器装置不兼容的格式或协议的全局存储器控制信号来控制分立存储器装置。 分立存储器设备可以是商用的现成存储器设备或响应于本地或本地存储器控制信号的定制存储器设备。 全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。 复合存储器件包括包含分立存储器件和桥接器件的半导体管芯的系统级封装，或者可以包括具有封装的分立存储器件和安装在其上的封装桥接器件的印刷电路板。

    A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM
    2.
    发明申请
    A COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 审中-公开
    具有用于将分离存储器件连接到系统的桥接器件的复合存储器

    公开(公告)号：WO2010043032A1

    公开(公告)日：2010-04-22

    申请号：PCT/CA2009/001451

    申请日：2009-10-14

    Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki ,  PYEON, Hong, Beom

    Inventor： KIM, Jin-Ki ,  PYEON, Hong, Beom

    IPC: G11C7/10 ,  G11C16/06 ,  G11C5/06 ,  G11C7/22

    CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C5/025

    Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

    Abstract translation: 一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。 分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。 全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。 复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

    FLASH MEMORY PROGRAM INHIBIT SCHEME
    4.
    发明申请
    FLASH MEMORY PROGRAM INHIBIT SCHEME 审中-公开
    闪存存储器程序禁止方案

    公开(公告)号：WO2008064480A1

    公开(公告)日：2008-06-05

    申请号：PCT/CA2007/002149

    申请日：2007-11-29

    Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

    Inventor： KIM, Jin-Ki

    IPC: G11C7/12 ,  G11C16/24

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3427

    Abstract: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

    Abstract translation: 一种用于最小化闪存中程序干扰的方法。 为了减少在不需要擦除状态的编程的NAND闪存单元串中的程序干扰，使用局部增强的通道抑制方案。 在本地提升通道禁止方案中，在NAND串中未选择编程的NAND串中选择的存储单元与NAND串中的其它单元解耦。 这使得解耦单元的通道在相应的字线升高到编程电压时被局部提升到足以抑制F-N隧穿的电压电平。 由于高的提升效率，相对于现有技术的方案，可以减少施加到NAND串中的剩余存储单元的栅极的通过电压，从而最小化程序干扰同时允许随机页面编程。

    SCALABLE MEMORY SYSTEM
    5.
    发明申请
    SCALABLE MEMORY SYSTEM 审中-公开
    可扩展存储系统

    公开(公告)号：WO2008022454A1

    公开(公告)日：2008-02-28

    申请号：PCT/CA2007/001469

    申请日：2007-08-22

    Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki ,  OH, HakJune ,  PYEON, Hong Beom ,  PRZYBYLSKI, Steven

    Inventor： KIM, Jin-Ki ,  OH, HakJune ,  PYEON, Hong Beom ,  PRZYBYLSKI, Steven

    IPC: G11C7/10 ,  G11C5/14 ,  G11C8/18

    CPC classification number: G11C7/1042 ,  G11C7/10 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/20 ,  G11C8/04 ,  G11C16/0483

    Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

    Abstract translation: 存储器系统架构具有串行连接的存储器件。 内存系统是可扩展的，可以包括任何数量的内存设备，而不会造成任何性能下降或重新设计。 每个存储器件具有用于在其他存储器件和存储器控制器之间通信的串行输入/输出接口。 存储器控制器在至少一个比特流中发出命令，其中比特流遵循模块化命令协议。 该命令包括具有可选地址信息和设备地址的操作代码，使得只有寻址的存储器件对该命令起作用。 分别提供与每个输出数据流和输入命令数据流并行提供的数据输出选通信号和命令输入选通信号，用于识别数据的类型和数据的长度。 模块化命令协议用于在每个存储设备中执行并发操作，以进一步提高性能。

    FLASH MEMORY SYSTEM CONTROL SCHEME
    6.
    发明申请
    FLASH MEMORY SYSTEM CONTROL SCHEME 审中-公开
    闪存存储器系统控制方案

    公开(公告)号：WO2007112555A1

    公开(公告)日：2007-10-11

    申请号：PCT/CA2007/000501

    申请日：2007-03-29

    Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

    Inventor： KIM, Jin-Ki

    IPC: G11C7/10 ,  G11C11/4193 ,  G11C16/00

    CPC classification number: G11C7/1042 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C7/1021 ,  G11C16/10 ,  G11C16/32 ,  G11C2216/22 ,  G11C2216/24

    Abstract: A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.

    Abstract translation: 闪存系统架构具有串行连接的闪存设备，以实现数据的高速编程。 通过将要编程的数据的页面交织在系统中的存储器件中来实现数据的高速编程，使得不同的数据页被存储在不同的存储器件中。 存储器控制器为每个存储器件发出程序命令。 当每个存储器件接收到程序命令时，它开始编程操作或将命令传递到下一个存储器件。 因此，闪存系统中的存储器件一个接一个地顺序地编程数据页面，从而最小化将每一页数据编程到闪存系统中的延迟。 存储器控制器可以执行磨损均衡算法以最大化每个存储器件的耐久性，或优化任何尺寸的数据的编程性能和耐久性。

    WRITE SCHEME IN PHASE CHANGE MEMORY
    9.
    发明申请
    WRITE SCHEME IN PHASE CHANGE MEMORY 审中-公开
    相变记忆中的写入方案

    公开(公告)号：WO2011134055A1

    公开(公告)日：2011-11-03

    申请号：PCT/CA2011/000472

    申请日：2011-04-26

    Applicant: MOSAID TECHNOLOGIES INCORPORATED ,  KIM, Jin-Ki

    Inventor： KIM, Jin-Ki

    IPC: G11C7/00 ,  G11C13/00 ,  G11C7/22

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/0061 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0088 ,  G11C2213/72

    Abstract: In a phase change memory, an input data corresponding to a plurality of memory cells is received and a previous data is read from the plurality of memory cells. The input data is compared with the previous data. In the case where the input data is different from the previous data for one or more of the plurality of memory cells and a write count is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the write count is updated or incremented. Such operations of data comparison and update of the write count are repeated. If the write count reaches the maximum value, it will be determined that the writing is falied.

    Abstract translation: 在相变存储器中，接收对应于多个存储单元的输入数据，并从多个存储单元读取先前的数据。 将输入数据与先前的数据进行比较。 在输入数据与多个存储单元中的一个或多个的先前数据不同且写入数小于最大值的情况下，多个存储器单元中的一个或多个用输入数据编程，并且 写入计数更新或增加。 重复数据比较和更新写入次数的这种操作。 如果写入计数达到最大值，则会确定写入是否成功。

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