公开(公告)号：WO03007348A3

公开(公告)日：2003-08-21

申请号：PCT/US0222106

申请日：2002-07-11

Applicant: LAM RES CORP ,  BOYD JOHN M ,  RAVKIN MIKE ,  MIKHAYLICH KATRINA A

Inventor： BOYD JOHN M ,  RAVKIN MIKE ,  MIKHAYLICH KATRINA A

IPC: H01L21/304 ,  H01L21/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L21/02057 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/67028 ,  H01L21/67034 ,  Y10S134/902

Abstract: A method and apparatus for controlling galvanic corrosion effects on a single-wafer cleaning system are provided. In one embodiment, a method for minimizing galvanic corrosion effects in a single-wafer cleaning system is provided. The method initiates with applying a cleaning chemistry containing corrosion inhibitors to a surface of a wafer. Then, the surface of the wafer is exposed to the cleaning chemistry for a period of time. Next, a concentration gradient at an interface of the cleaning chemistry and the surface of the wafer is refreshed. Then, a rinsing agent and a drying agent are applied simultaneously to remove the cleaning chemistry , wherein the drying agent dries the surface of the wafer prior to a concentration of the corrosion inhibitors being diluted to a level insufficient to provide corrosion protection.

Abstract translation: 提供了一种用于控制对单晶片清洁系统的电偶腐蚀影响的方法和装置。 在一个实施例中，提供了一种用于最小化单晶片清洁系统中的电偶腐蚀效应的方法。 该方法通过将包含腐蚀抑制剂的清洁化学品施加到晶片的表面来启动。 然后，将晶片的表面暴露于清洁化学品一段时间。 接下来，刷新清洁化学品和晶片表面的界面处的浓度梯度。 然后，同时施加漂洗剂和干燥剂以除去清洁化学品，其中干燥剂在将腐蚀抑制剂的浓度稀释至不足以提供防腐蚀的水平之前将晶片的表面干燥。

公开(公告)号：WO2003060962A3

公开(公告)日：2003-07-24

申请号：PCT/US2002/040754

申请日：2002-12-20

Applicant: APPLIED MATERIALS, INC.

Inventor： DUBOUSE, Alain ,  LIU, Feng, Q. ,  WANG, Yan ,  CHEN, Liang-Yuh ,  SUN, Lizhong ,  WANG, Yuchun ,  NEO, Siew

IPC: H01L21/321

Abstract: An electrolyte composition and method for planarizing a surface of a wafer using the electrolyte composition is provided. In one aspect, the electrolyte composition includes ammonium dihydrogen phosphate, diammonium hydrogen phosphate, or a mixture thereof. The composition has a pH between about 3 and about 10 which is environmentally friendly and does not present hazardous operation concerns. The composition may further comprise one or more additives selected from a group consisting of benzotriazole, ammonium citrate, ethlylenediamine, tetraethylenepentamine, triethylenetetramine, diethylenetriamine, amino acids, ammonium oxalate, ammonia, ammonium succinate, and citric acid.

公开(公告)号：WO03017330A3

公开(公告)日：2003-07-24

申请号：PCT/US0226167

申请日：2002-08-15

Applicant: ACM RES INC ,  YAO XIANG YU ,  CHANG RU KAO ,  YIH PEIHAUR ,  WANG HUI

Inventor： YAO XIANG YU ,  CHANG RU KAO ,  YIH PEIHAUR ,  WANG HUI

IPC: C25F3/22 ,  B23H5/08 ,  B24B37/04 ,  C25F3/16 ,  C25F3/30 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52

CPC classification number: C25F3/16 ,  B23H5/08 ,  B24B37/04 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for planarizing and electropolishing a conductive layer on a semiconductor structure includes forming a dielectric layer with recessed areas and non-recessed areas on the semiconductor wafer. A conductive layer is formed over the dielectric layer to cover the recessed areas and non-recessed areas. The surface of the conductive layer is then planarized to reduce variations in the topology of the surface. The planarized conductive layer is then electropolished to expose the non-recessed area.

Abstract translation: 一种用于平坦化和电抛光半导体结构上的导电层的方法包括在半导体晶片上形成具有凹陷区域和非凹陷区域的电介质层。 在介电层上形成导电层以覆盖凹陷区域和非凹陷区域。 然后平面化导电层的表面以减少表面拓扑的变化。 然后将平面化的导电层电抛光以暴露非凹陷区域。

公开(公告)号：WO02075804A3

公开(公告)日：2003-06-26

申请号：PCT/US0204806

申请日：2002-02-19

Applicant: APPLIED MATERIALS INC

Inventor： CHEN LIANG-YUH ,  HSU WEI-YUNG ,  DUBOUST ALAIN ,  MORAD RATSON ,  CARL DANIEL A ,  SOMEKH SASSON ,  MAYDAN DAN

IPC: B24B37/00 ,  B23H5/08 ,  B24B37/04 ,  H01L21/304 ,  H01L21/316 ,  H01L21/321

CPC classification number: B23H5/08

Abstract: A method and apparatus are provided for planarizing a material layer on a substrate. In one aspect, a method is provided for processing a substrate including forming a passivation layer on a substrate surface, polishing the substrate in an electrolyte solution, applying an anodic bias to the substrate surface, and removing material from at least a portion of the substrate surface. In another aspect, an apparatus is provided which includes a partial enclosure, polishing article, a cathode, a power source, a substrate carrier movably disposed above the polishing article, and a computer based controller to position a substrate in an electrolyte solution to form a passivation layer on a substrate surface, to polish the substrate in the electrolyte solution with the polishing article, and to apply an anodic bias to the substrate surface or polishing article to remove material from at least a portion of the substrate surface.

Abstract translation: 提供了一种用于平坦化衬底上的材料层的方法和装置。 在一个方面，提供一种用于处理衬底的方法，包括在衬底表面上形成钝化层，在电解质溶液中抛光衬底，向衬底表面施加阳极偏压，以及从衬底的至少一部分去除材料 表面。 在另一方面，提供了一种装置，其包括部分外壳，抛光制品，阴极，电源，可移动地设置在抛光制品上方的基板载体，以及基于计算机的控制器，以将基板定位在电解质溶液中以形成 在衬底表面上的钝化层，用抛光制品抛光电解质溶液中的衬底，并将阳极偏压施加到衬底表面或抛光制品上以从衬底表面的至少一部分去除材料。

公开(公告)号：WO2003050864A2

公开(公告)日：2003-06-19

申请号：PCT/US2002/041453

申请日：2002-12-03

Applicant: CABOT MICROELECTRONICS CORPORATION

Inventor： SCHROEDER, David, J. ,  CARTER, Phillip ,  CHAMBERLAIN, Jeffrey, P. ,  MILLER, Kyle ,  CHERIAN, Isaac, K.

IPC: H01L21/321

CPC classification number: C23F3/06 ,  C09G1/02 ,  C09K3/1436 ,  C09K3/1463 ,  H01L21/3212

Abstract: The invention provides a method of polishing a substrate comprising a metal layer comprising copper. The method comprises the steps of (i) providing a chemical-mechanical polishing system comprising a liquid carrier, a polishing pad, an abrasive, and a negatively charged polymer or copolymer, (ii) contacting the substrate with the polishing system, and (iii) abrading at least a portion of the substrate to polish the metal layer of the substrate. The negatively charged polymer or copolymer comprises one or more monomers selected from sulfonic acids, sulfonates, sulfates, phosphonic acids, phosphonates, and phosphates, has a molecular weight of 20,000 g/mol or more, and coats at least a portion of the abrasive such that the abrasive has a zeta potential value that is lowered upon interaction of the negatively charged polymer or copolymer with the abrasive.

Abstract translation: 本发明提供一种抛光包含含铜金属层的基材的方法。 该方法包括以下步骤：（i）提供包含液体载体，抛光垫，研磨剂和带负电的聚合物或共聚物的化学机械抛光系统，（ii）使基材与抛光系统接触，以及（iii） ）研磨至少一部分基板以抛光基板的金属层。 带负电荷的聚合物或共聚物包含选自磺酸，磺酸盐，硫酸盐，膦酸，膦酸盐和磷酸盐中的一种或多种单体，其分子量为20,000g / mol或更高，并且将至少一部分磨料 研磨剂的ζ电位值在负电荷聚合物或共聚物与研磨剂相互作用时降低。

公开(公告)号：WO02092211A3

公开(公告)日：2003-05-30

申请号：PCT/US0207844

申请日：2002-03-12

Applicant: 3M INNOVATIVE PROPERTIES CO

Inventor： LAMANNA WILLIAM M ,  SAVU PATRICIA M ,  PARENT MICHAEL J ,  ZAZZERA LAWRENCE A

IPC: C11D1/02 ,  B01F17/00 ,  C07C217/08 ,  C07C311/03 ,  C09G1/02 ,  C09K3/14 ,  C09K13/08 ,  C10M105/74 ,  C10M135/08 ,  C10M135/10 ,  C10M137/04 ,  C10M169/04 ,  C10N40/08 ,  C25D3/02 ,  C25D3/38 ,  H01L21/02 ,  H01L21/321 ,  C10N30/00 ,  C23F1/16 ,  C23F1/32 ,  C25D3/10 ,  C25F3/30 ,  C01M169/04

CPC classification number: C09K13/08 ,  B01F17/0057 ,  C09G1/02 ,  C09K3/1463 ,  C10M135/10 ,  C10M169/04 ,  C10M2207/026 ,  C10M2207/027 ,  C10M2207/28 ,  C10M2209/084 ,  C10M2215/06 ,  C10M2219/044 ,  C10M2223/0405 ,  C10M2229/041 ,  C10N2210/01 ,  C10N2230/24 ,  C10N2240/08 ,  C25D3/02 ,  C25D3/38 ,  H01L21/02052 ,  H01L21/3212 ,  Y10T428/3154

Abstract: The present invention provides for the use of bis(perfluoroalkanesulfonyl)imide and its salts as surfactants or additives applications having an extreme environment.

Abstract translation: 本发明提供了双（全氟烷基磺酰基）酰亚胺及其盐作为具有极端环境的表面活性剂或添加剂应用的用途。

公开(公告)号：WO02059962A3

公开(公告)日：2003-04-17

申请号：PCT/US0201692

申请日：2002-01-22

Applicant: HONEYWELL INT INC

Inventor： MUKHERJEE SHYAMA ,  DEBEAR DONALD ,  LEVERT JOSEPH

IPC: C23F1/02 ,  C23F1/18 ,  C23F3/06 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/32115 ,  C23F3/06 ,  H01L21/32134 ,  H01L21/7684 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S977/712 ,  Y10S977/788 ,  H01L2924/00

Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer (13) tending to dwell in regions of lower surface topography (8, 9, 10), protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer. In some embodiments of the present invention, the viscous overlayer may be added prior to the introduction of etchant to the wafer surface, or both etchant and viscous overlayer may be introduced substantially simultaneously, typically as the wafer is spun during planarization.

Abstract translation: 本发明涉及通常在集成电路的制造中遇到的表面的平坦化，特别是在镶嵌和双镶嵌互连中遇到的铜导体和Ta / TaN阻挡层。 本发明描述了用于Cu / Ta / TaN互连的平坦化方法，通常使用倾向于驻留在下表面形貌（8,9,10）的区域中的粘性覆层（13），通过组合保护所述下部区域免受蚀刻 的化学和机械效应。 在一些实施方案中，粘性覆层包含妨碍从与粘性层接触的表面区域去除铜的物质。 这样的物质可以是其他添加剂中基本饱和的铜离子溶液，从而阻碍互连铜溶解到保护性覆盖层中。 在本发明的一些实施方案中，可以在将蚀刻剂引入晶片表面之前添加粘性覆层，或者基本上同时引入蚀刻剂和粘性覆盖层，通常当平坦化期间晶片旋转时。

公开(公告)号：WO0185392A3

公开(公告)日：2002-10-10

申请号：PCT/US0115205

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIN CHENTING ,  PLOESSL ROBERT

IPC: B24B20060101 ,  B24B7/24 ,  B24B37/04 ,  H01L21/302 ,  H01L21/304 ,  H01L21/321 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/7684

Abstract: A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines (17) in trenches in an insulation (oxide) layer (12) of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer (15) disposed on the oxide layer (12) and having a lower portion located in the trenches (13) for forming metal lines and an upper portioN (18) overlying the lower portion (16). The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion (18) while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion (18) without dishing of the metal layer lower portion (16) in the trenches (13). The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion (18) with minimized (reduced) dishing of the metal layer lower portion (16) to an extent providing the metal lines (17) as individual metal lines (17) in the trenches (13). Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

Abstract translation: 提供两步化学机械抛光（CMP）工艺以在其制造期间使多个半导体晶片的绝缘（氧化物）层（12）中的沟槽中的金属线（17）的凹陷最小化（减少）。 对于每个晶片，第一步骤包括设置在氧化物层（12）上的金属层（15）的CMP，并且具有位于沟槽（13）中的下部，用于形成金属线，并且覆盖下部的上端口（18） 部分（16）。 第一步抛光使用第一抛光垫去除金属层上部（18）的主体，同时产生伴随的CMP残留物，并且使金属层上部（18）的最小（减少）余数不会金属脱落 沟槽（13）中的下层部分（16）。 第二步是用第二抛光垫继续CMP，以金属层下部（16）的最小化（减少）凹陷将金属层上部（18）的剩余部分移至提供金属线（17）的程度，以作为 沟槽（13）中的各个金属线（17）。 每个晶片用第一抛光垫进行第一步抛光，然后用第二抛光垫抛光第二步。 第二抛光垫至多具有先前累积的伴随的CMP残留物的不足量，例如是相对新鲜的（干净的）抛光垫。

公开(公告)号：WO2002075804A2

公开(公告)日：2002-09-26

申请号：PCT/US2002/004806

申请日：2002-02-19

Applicant: APPLIED MATERIALS, INC.

Inventor： CHEN, Liang-Yuh, ,  HSU, Wei-Yung, ,  DUBOUST, Alain ,  MORAD, Ratson ,  CARL, Daniel, A. ,  SOMEKH, Sasson ,  MAYDAN, Dan

IPC: H01L21/321

CPC classification number: B23H5/08

Abstract: A method and apparatus are provided for planarizing a material layer on a substrate. In one aspect, a method is provided for processing a substrate including forming a passivation layer on a substrate surface, polishing the substrate in an electrolyte solution, applying an anodic bias to the substrate surface, and removing material from at least a portion of the substrate surface. In another aspect, an apparatus is provided which includes a partial enclosure, polishing article, a cathode, a power source, a substrate carrier movably disposed above the polishing article, and a computer based controller to position a substrate in an electrolyte solution to form a passivation layer on a substrate surface, to polish the substrate in the electrolyte solution with the polishing article, and to apply an anodic bias to the substrate surface or polishing article to remove material from at least a portion of the substrate surface.

Abstract translation: 提供了一种用于平坦化衬底上的材料层的方法和装置。 在一个方面，提供一种用于处理衬底的方法，包括在衬底表面上形成钝化层，在电解质溶液中抛光衬底，向衬底表面施加阳极偏压，以及从衬底的至少一部分去除材料 表面。 在另一方面，提供了一种装置，其包括部分外壳，抛光制品，阴极，电源，可移动地设置在抛光制品上方的基板载体，以及基于计算机的控制器，以将基板定位在电解质溶液中以形成 在衬底表面上的钝化层，用抛光制品抛光电解质溶液中的衬底，并将阳极偏压施加到衬底表面或抛光制品上以从衬底表面的至少一部分去除材料。

公开(公告)号：WO2002065538A3

公开(公告)日：2002-08-22

申请号：PCT/US2002/003422

申请日：2002-02-06

Applicant: ESC, INC.

Inventor： NAGHSHINEH, Shahriar ,  BARNES, Jeff ,  OLDAK, Ewa, B.

IPC: H01L21/321

Abstract: A cleaning solution for cleaning microelectronic substrates, particularly for post-CMP or via formation cleaning. The cleaning solution comprises a quaternary ammonium hydroxide, an organic amine, a corrosion inhibitor, optionally an organic acid, and water. A preferred cleaning solution comprises tetramethylammonium hydroxide, monoethylanolamine, gallic acid ascorbic acid, and water with the alkalinity of the cleaning solution greater then 0.073 milliequivalents base per gram of solution.