公开(公告)号：WO2008014033A2

公开(公告)日：2008-01-31

申请号：PCT/US2007/068100

申请日：2007-05-03

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHOY, Jon S. ,  AKHTER, Tahmina

Inventor： CHOY, Jon S. ,  AKHTER, Tahmina

IPC: G11C5/14

CPC classification number: G11C29/02 ,  G11C7/04 ,  G11C7/062 ,  G11C7/14 ,  G11C16/28 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/063

Abstract: A memory (12) includes a plurality of memory cells (12), a sense amplifier (18) coupled to at least one of the plurality of memory cells, a temperature dependent current generator (26) comprising a plurality of selectable temperature dependent current sources (52-62) for generating a temperature dependent current, a temperature independent current generator (28) comprising a plurality of selectable temperature independent current sources (70, 72, 74) for generating a temperature independent current, and a summer (30) coupled to the temperature dependent current generator (26) and the temperature independent current generator (28) for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier (18). A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract translation: 存储器（12）包括多个存储器单元（12），耦合到所述多个存储器单元中的至少一个存储器单元的读出放大器（18），温度依赖性电流发生器（26），所述温度依赖性电流发生器 用于产生温度依赖电流的多个可选择温度依赖电流源（52-62），包括多个可选择温度独立电流源（70,72,74）的独立于温度的电流发生器（28），用于产生温度独立电流 ，以及耦合到温度依赖电流发生器（26）和温度独立电流发生器（28）的加法器（30），用于组合温度依赖电流和温度独立电流以生成供读出放大器（18）使用的参考电流 ）。 参考电流的温度系数与多个存储器单元中的至少一个存储器单元的存储器单元电流的温度系数大致相同。

公开(公告)号：WO2007002054A1

公开(公告)日：2007-01-04

申请号：PCT/US2006/023931

申请日：2006-06-19

Applicant: SANDISK 3D LLC ,  SCHEUERLEIN, Roy, E.

Inventor： SCHEUERLEIN, Roy, E.

IPC: G11C11/404

CPC classification number: G11C11/404 ,  G11C11/4076 ,  G11C2207/063

Abstract: A method is set forth for writing volatile memory cells embodied on an integrated circuit and taking the form of an array of volatile memory cells including a plurality of word lines and a plurality of bit lines. In use, a first write operation is performed on at least one memory cell at a first time. Further, at a second time, a second write operation is performed on at least one memory cell. During use, various voltage relationships may be employed for enhanced programming. Just by way of example, a voltage at a corresponding word line associated with the at least one memory cell during the first write operation is different than that during the second write operation.

Abstract translation: 提出了一种用于写入集成电路中实现的易失性存储单元并采取包括多个字线和多个位线的易失性存储单元阵列的形式的方法。 在使用中，在第一次对至少一个存储单元执行第一写入操作。 此外，在第二时间，对至少一个存储单元执行第二写入操作。 在使用期间，可以采用各种电压关系来增强编程。 仅作为示例，在第一写入操作期间与至少一个存储器单元相关联的对应字线处的电压与在第二写入操作期间的电压不同。

公开(公告)号：WO2006071684A3

公开(公告)日：2006-10-12

申请号：PCT/US2005046407

申请日：2005-12-20

Applicant: SPANSION LLC ,  AKAOGI TAKAO ,  WADHWA SAMEER ,  ACHTER MICHAEL ,  VENKATESH BHIMACHAR

Inventor： AKAOGI TAKAO ,  WADHWA SAMEER ,  ACHTER MICHAEL ,  VENKATESH BHIMACHAR

IPC: G11C7/06 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C2207/063 ,  H03F3/345 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/462 ,  H03F2200/78

Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Abstract translation: 读出放大器包括用于产生参考输出电压的参考电压发生器和用于产生核心输出电压的核心输出电压发生器。 核心输出电压发生器包括核心前端级和核心后端级，或者包括多个放大器晶体管，每个放大器晶体管通过诸如核心单元的电流传导器件导通一部分芯电流。 这种组件的晶体管的尺寸和/或连接导致高电压摆动，从而导致读出放大器的高灵敏度。

公开(公告)号：WO2006062113A1

公开(公告)日：2006-06-15

申请号：PCT/JP2005/022425

申请日：2005-12-07

Applicant: TDK株式会社 ,  江▲崎▼ 城一朗 ,  柿沼 裕二

Inventor： 江▲崎▼ 城一朗 ,  柿沼 裕二

IPC: G11C11/15

CPC classification number: G11C11/16 ,  G11C7/062 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2207/063

Abstract: 　より低い電源電圧であっても情報の読み出しを行い得る磁気メモリデバイスを提供する。 　（ｉ＋１）行（ｊ＋１）列（ｉ，ｊは１以上の整数）で二次元状に配列された複数の記憶セル１を備えた磁気メモリデバイスであって、各記憶セル１には、２つの磁気抵抗効果発現体２ａ，２ｂがそれぞれ配設され、磁気抵抗効果発現体２ａ，２ｂの抵抗値を感知するための電流Ｉｂ１，Ｉｂ２を供給する前段回路４１と、磁気抵抗効果発現体２ａ，２ｂに電流Ｉｗ１，Ｉｗ２を供給するＸ方向アドレスデコーダ回路３２と、電流Ｉｂ１と電流Ｉｗ１との合計値、および電流Ｉｗ２と電流Ｉｂ２との合計値をそれぞれ一定に制御する電流制御回路（定電流回路２５ｎ）とを備えている。

Abstract translation: 即使在较低的电源电压下也能够读取信息的磁存储器件。 磁存储器件包括排列成（i + 1）行和（j + 1）列（i和j：1或更大的整数）的二维形状的多个存储单元（1）。 每个存储单元（1）包括具有分别布置在其中的两个磁阻效应表示器（2a，2b）的前级电路（41），用于馈送电流（Ib1，Ib2）以感测磁阻效应显示器的电阻 2a，2b），用于将电流（Iw1，Iw2）馈送到磁阻效果器（2a，2b）的X方向地址解码器电路（32）和电流控制电路（恒流电路） 用于将电流（Ib1）和电流（Iw1）之和和电流（Iw2）和电流（Ib2）之和分别控制为常数值。

公开(公告)号：WO2004086406A8

公开(公告)日：2006-04-20

申请号：PCT/NO2004000086

申请日：2004-03-25

Applicant: THIN FILM ELECTRONICS ASA ,  SCHWEICKERT ROBERT ,  LEISTAD GEIRR I

Inventor： SCHWEICKERT ROBERT ,  LEISTAD GEIRR I

IPC: G11C20060101 ,  G11C7/06 ,  G11C11/22 ,  G11C16/06

CPC classification number: G11C7/062 ,  G11C11/22 ,  G11C2207/063

Abstract: A sense amplifier system for sensing the charge of a charge-­storing means (601) comprises a first and second charge reference means (600a, 600b) connected in parallel and similar to the charge-storing means (601) and having respectively opposite polarization. The charge reference means (600a, 600b) and the charge-storing means (601) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA1, RSA2) are connected with output nodes (RBL1, RBL2) of the charge reference means (600a, 600b) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo-differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means (601) and generates an output signal indicative of a polarization state of the charge-storing means. Another embodiment adapted for sensing the charges of a plurality of charge-storing means (701) and comprising at least two pairs of charge reference means is also described. A non-volatile matrix-addressable memory system comprising an electrical polarizable dielectric memory material exhibiting hysterisis and a sense amplifier system as described is also claimed.

Abstract translation: 用于感测电荷存储装置（601）的电荷的感测放大器系统包括并联连接并类似于电荷存储装置（601）并具有相反偏振的第一和第二电荷参考装置（600a，600b）。 充电参考装置（600a，600b）和电荷存储装置（601）具有公共输入节点（WL），并且第一和第二伪差分参考读出放大器（RSA1，RSA2）与输出节点（RBL1， 用于将参考信号产生到与伪差分读出放大器（SA）连接的公共参考节点（CHREF）的电荷参考装置（600a，600b）的RBL2）。 伪差分读出放大器（SA）具有用于从电荷存储装置（601）接收输出信号的第二输入端，并产生指示电荷存储装置的极化状态的输出信号。 还描述了适于感测多个电荷存储装置（701）的电荷并且包括至少两对电荷参考装置的另一实施例。 还要求保护包括表现迟滞的电极化电介质存储材料和所述读出放大器系统的非易失性矩阵寻址存储器系统。

公开(公告)号：WO2006027373A1

公开(公告)日：2006-03-16

申请号：PCT/EP2005/054430

申请日：2005-09-07

Applicant: INFINEON TECHNOLOGIES AG ,  GOGL, Dietmar ,  VIEHMANN, Hans-Heinrich

Inventor： GOGL, Dietmar ,  VIEHMANN, Hans-Heinrich

IPC: G11C7/06 ,  G11C11/16

CPC classification number: G11C7/04 ,  G11C7/02 ,  G11C7/062 ,  G11C7/067 ,  G11C11/16 ,  G11C2207/063

Abstract: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

Abstract translation: 高速电流检测放大器具有补充参考电池和负载装置，可消除电容失配的贡献。 电流检测放大器包括电压比较器，耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置。 第一夹紧装置耦合到参考电压。 第二钳位装置耦合在电压比较器的第二输入端和第二输入信号节点之间。 第二钳位装置也耦合到参考电压。 电流镜耦合在电压比较器的第一和第二输入端之间并耦合到有源电容平衡电路。 有源电容平衡电路可以与电压比较器组合。 均衡装置可以耦合在电压比较器的第一和第二输入之间，以及第一输入信号节点和第二输入信号节点之间。

公开(公告)号：WO2004034440A3

公开(公告)日：2004-11-11

申请号：PCT/US0332432

申请日：2003-10-14

Applicant: FAIRCHILD SEMICONDUCTOR

Inventor： CRAIN ETHAN A ,  RAPP KARL ,  SHACHAM ETAN

IPC: G01R19/00 ,  G06K17/00 ,  G11C7/02 ,  G11C7/06 ,  G11C16/26 ,  H01L20060101 ,  H03K5/153 ,  H03K5/22 ,  H04B5/02

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C2207/063

Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, io with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

Abstract translation: 公开了一种非常适合低频RFID系统的低读电流低功耗读出放大器。 MOS晶体管从存储单元（通常为EEPROM）接收读取电流，电流镜由并联MOS晶体管形成。 电容器上的电荷通过复位脉冲清零后，镜电流集成在电容上。 定义一个时间段，在该时间段期间将电容器上的电压与第二电压进行比较。 第二电压由参考电压或虚设单元形成，在任一种情况下，参考电压约为存储在存储单元中的一个和零之间的逻辑边界。 具有或没有输入滞后的比较器io接收电容器上的电压和第二电压，并且在该时间段内，比较器的输出状态指示存储器单元的二进制内容。

公开(公告)号：WO2004003919A1

公开(公告)日：2004-01-08

申请号：PCT/US2003/013007

申请日：2003-04-24

Applicant: MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE

Inventor： SUBRAMANIAN, Chitra, K. ,  GARNI, Bradley, J. ,  NAHAS, Joseph, J. ,  LIN, Halbert, S. ,  ANDRE, Thomas, W.

IPC: G11C7/06

CPC classification number: G11C7/18 ,  G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C2207/005 ,  G11C2207/063

Abstract: A memory (10) provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier (24) and the route the reference or references take to the sense amplifier. Each sub-array (14, 18) of the memory has an adjacent column decoder (20, 22) that couples data to a data line (37, 51, 41, 63) that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier (24) that is impedance balanced with respect to the route taken by the data.

Abstract translation: 存储器（10）提供了一种感测方案，其保持数据到读出放大器（24）的路线与参考或参考取向读出放大器的路线之间的阻抗平衡。 存储器的每个子阵列（14,18）具有将数据耦合到也与子阵列相邻的数据线（37,51,41,63）的相邻列解码器（20,22），并且可以是 被视为列解码器的一部分。 所选子阵列的数据通过其相邻数据线路由到读出放大器。 作为所选子阵列的一部分的参考被耦合到未选择的子阵列的数据线。 因此，在MRAM型存储器的情况下，参考优选地紧邻所选数据的位置，穿过到相对于由数据采取的路由阻抗平衡的读出放大器（24）的路由。

公开(公告)号：WO02078003A3

公开(公告)日：2003-08-07

申请号：PCT/US0208675

申请日：2002-03-21

Applicant: MATRIX SEMICONDUCTOR INC

Inventor： SCHEUERLEIN ROY E

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C13/0069 ,  G11C5/025 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/0028 ,  G11C17/16 ,  G11C17/18 ,  G11C2013/0092 ,  G11C2207/063 ,  G11C2213/72 ,  G11C2213/73

Abstract: A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

Abstract translation: 无源元件存储器阵列优选地将所选择的X线偏置到外部接收的VPP电压，并将选定的Y线偏置到地。 未选择的Y线优选地偏置到VPP减去第一偏移电压，并且偏置到第二偏移电压（相对于地）的未选择的X线。 第一和第二偏移电压优选地相同并且具有约0.5至2伏特的值。 VPP电压取决于所使用的存储器单元技术，优选落在5至20伏的范围内。 片上VPP发生器所需的区域，并节省了这种发电机将消耗的功率。 此外，编程操作期间集成电路的工作温度降低，这进一步降低了功耗。 当放电存储器阵列时，层间的电容最好首先放电，然后将这些层放电到地。

公开(公告)号：WO02013198A1

公开(公告)日：2002-02-14

申请号：PCT/EP2001/008667

申请日：2001-07-26

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C2207/063

Abstract: The invention relates to a high speed sense amplifier with low power draw for a memory cell (1). The sense amplifier comprises a first current balancing circuit (53, 55) which amplifies a memory signal current (IBL) received from the memory cell (1) over a memory signal line (3) and delivers the result to a signal output (16) on the sense amplifier (11), a second current balancing circuit (53, 54) which generates an adjustable current (IEINSTELL) depending on the received memory signal current (IBL) and an adjustable reference current source (23) which supplies a reference current (IREF) to the signal output (20) on the sense amplifier (11). The value of the supplied reference current (IREF) may be adjusted as a function of the adjustable current (IEINSTELL) generated by the second current balancing circuit (53, 54) by means of an adjustment line (28).

Abstract translation: 高速读出电流放大器具有低功率消耗的存储单元（1），其中，所述感测电流放大器，第一电流镜电路（53，55），存储单元（1）经由存储器信号线接收到的（3）存储器的信号电流（IBL），以扩增的一个 发射感测电流放大器的信号输出（16）（11），其具有在所接收的存储器信号电流（IBL）依赖性的设定电流（IEINSTELL）的第二电流反射镜电路（53，54）被产生，并具有可调节的基准电流源（23） 该基准电流（IREF）传送到感测电流放大器的信号输出（20）（11），其中产生经调整线设定电流（IEINSTELL）通过所述第二电流镜电路（53，54）中的依赖性输出基准电流（IREF）的高度 （28）是可调的。