公开(公告)号：WO2008089158A3

公开(公告)日：2009-12-30

申请号：PCT/US2008051024

申请日：2008-01-14

Applicant: ATMEL CORP ,  BEDARIDA LORENZO ,  PELLI GABRIELE ,  BARTOLI SIMONE ,  CHINOSI MAURO

Inventor： BEDARIDA LORENZO ,  PELLI GABRIELE ,  BARTOLI SIMONE ,  CHINOSI MAURO

IPC: G11C7/08

CPC classification number: G11C7/062 ,  G11C7/02 ,  G11C7/067 ,  G11C16/26 ,  G11C2207/063

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract translation: 具有电流偏移功能的感测电路。 在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。 感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。 感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。 根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

公开(公告)号：WO2008089158A2

公开(公告)日：2008-07-24

申请号：PCT/US2008/051024

申请日：2008-01-14

Applicant: ATMEL CORPORATION ,  BEDARIDA, Lorenzo ,  PELLI, Gabriele ,  BARTOLI, Simone ,  CHINOSI, Mauro

Inventor： BEDARIDA, Lorenzo ,  PELLI, Gabriele ,  BARTOLI, Simone ,  CHINOSI, Mauro

IPC: G11C7/08

CPC classification number: G11C7/062 ,  G11C7/02 ,  G11C7/067 ,  G11C16/26 ,  G11C2207/063

Abstract: A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.

Abstract translation: 具有电流偏移功能的感测电路。 在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。 感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。 感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。 根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

公开(公告)号：WO2008076307A1

公开(公告)日：2008-06-26

申请号：PCT/US2007/025501

申请日：2007-12-13

Applicant: ADVANCED MICRO DEVICES, INC. ,  DREESEN, Michael, A. ,  WUU, John, J. ,  WEISS, Donald, R.

Inventor： DREESEN, Michael, A. ,  WUU, John, J. ,  WEISS, Donald, R.

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/404

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C11/404 ,  G11C11/4091 ,  G11C2207/063 ,  G11C2211/4016

Abstract: A memory device (100) includes a memory array (102) and a sense amplifier (108). The memory array (102) includes a floating body cell (320, 420) configured to store a bit value. The sense amplifier (108) includes a bit output configured to provide an output voltage representative of the bit value and a reference source (302) configured to provide a reference voltage. The sense amplifier (108) further includes a current mirror (330, 430) configured to provide a current to the first floating body cell (320, 420) based on the reference voltage, and a differential amplifier circuit (332, 432) configured to determine the output voltage based on the reference voltage and a voltage across the floating body cell (320, 420) resulting from application of the current to the floating body cell (320, 420).

Abstract translation: 存储器件（100）包括存储器阵列（102）和读出放大器（108）。 存储器阵列（102）包括被配置为存储位值的浮动体单元（320,420）。 读出放大器（108）包括被配置为提供表示比特值的输出电压的比特输出和被配置为提供参考电压的参考源（302）。 读出放大器（108）还包括被配置为基于参考电压向第一浮动体单元（320,420）提供电流的电流镜（330,430），以及差分放大器电路（332,432），被配置为 基于参考电压和通过将电流施加到浮动体单元（320,420）而导致的浮体单元（320,420）两端的电压确定输出电压。

公开(公告)号：WO2007122564A3

公开(公告)日：2008-01-10

申请号：PCT/IB2007051414

申请日：2007-04-19

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  STORMS MAURITS M N

Inventor： STORMS MAURITS M N

IPC: G11C11/4091 ,  G11C7/06

CPC classification number: G11C7/067 ,  G11C2207/063 ,  G11C2207/065

Abstract: The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), The sense amplifier (SA) comprises a first module (M1) and a second module (M2). The first module (M1) provides a first current limited to a maximum value (Iref+Ibias). The second module (M2) provides a second current which decreases from a value higher than the maximum value at the start of a sensing operation until a value lower than the maximum value at the end of the sensing operation. The memory circuit has a third module (CS2) for sinking a third current (Ibias) at a side of the switching device (T2) coupled to the memory element (T1).

Abstract translation: 存储器电路包括用于感测存储元件（T1）的状态的至少一个存储元件（T1），读出放大器（SA），用于选择性地将读出放大器（SA）耦合到存储元件 （T1），读出放大器（SA）包括第一模块（M1）和第二模块（M2）。 第一模块（M1）提供限于最大值（Iref + Ibias）的第一电流。 第二模块（M2）提供第二电流，其从感测操作开始时的高于最大值的值减小到在感测操作结束时低于最大值的值。 存储器电路具有用于吸收耦合到存储元件（T1）的开关器件（T2）侧的第三电流（Ibias）的第三模块（CS2）。

公开(公告)号：WO2007059402A2

公开(公告)日：2007-05-24

申请号：PCT/US2006060705

申请日：2006-11-09

Applicant: ACTEL CORP ,  LEE POONGYEUB ,  LIU MINGCHI MITCH

Inventor： LEE POONGYEUB ,  LIU MINGCHI MITCH

IPC: H03M7/34

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C16/24 ,  G11C2207/12

Abstract: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to- voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current- to- voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

Abstract translation: 闪存阵列包括施加参考电流的参考位线。 在读取操作期间，选择用于读取的位线连接到电流 - 电压转换器，每个转换器基于在位线中流动的输入电流产生输出电压。 将电流 - 电压转换器的输出电压与从参考电流 - 电压转换器的输出导出的参考电压进行比较，该参考电压的输入由参考位线上的参考电流驱动。 任何传导比参考电流更多电流的单元将被视为已擦除单元。 相反，传导比参考电流更小电流的任何单元将被视为编程单元。

公开(公告)号：WO2004029984A3

公开(公告)日：2004-12-23

申请号：PCT/US0329603

申请日：2003-09-23

Applicant: SANDISK CORP

Inventor： CERNEA RAUL-ADRIAN ,  LI YAN

IPC: G11C7/00 ,  G11C7/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/28

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C11/5642 ,  G11C16/26

Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.

Abstract translation: 源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。 在感测期间，存储器单元的控制栅极电压被跨过电阻的电压降错误地偏置。 当通过接地回路的电流减小时，该误差被最小化。 用于减少源极偏置的方法是通过具有用于多通感测的特征和技术的读/写电路实现的。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。 以这种方式，关闭操作不会影响感测操作。 在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。 在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。

公开(公告)号：WO2004057619A1

公开(公告)日：2004-07-08

申请号：PCT/EP2003/014420

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DEBROSSE, John ,  GOGL, Dietmar ,  REOHR, William, Robert

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C2207/063

Abstract: A symmetrical high-speed current sense amplifier (44) having complementary reference cells and configurable load devices (42) that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier (44) is adapted for use in a symmetric sensing architecture and includes a configurable current mirror (36). The current sense amplifier includes a voltage comparator (34), a first clamping device (T1) coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clampling device (T2) is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. A current mirror (36) is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the current mirror may be hard-wired, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads (42) may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator (T4), and between the first input signal and the second input signal (T3).

Abstract translation: 具有互补参考单元和可配置负载设备（42）的对称高速电流检测放大器（44），其消除了架构相关的电容失配贡献。 电流感测放大器（44）适于在对称感测架构中使用并且包括可配置电流镜（36）。 电流感测放大器包括电压比较器（34），耦合在电压比较器的第一输入端和第一输入信号之间的第一钳位装置（T1），第一钳位装置耦合到参考电压。 第二取样装置（T2）耦合在电压比较器的第二输入端和第二输入信号之间，第二钳位装置耦合到参考电压。 电流镜（36）耦合在电压比较器的第一和第二输入端之间。 电流镜可以通过选择晶体管来配置。 或者，电流镜可以是硬连线的，并且可以使用多路复用器来选择第一输入信号还是第二输入信号连接到电流镜的第一或第二侧。 可以在适当的节点添加可配置的虚拟负载（42），以优化容性负载并增加放大器的速度。 均衡装置可以耦合在电压比较器（T4）的第一和第二输入端之间以及在第一输入信号和第二输入信号（T3）之间。

公开(公告)号：WO2004034400A3

公开(公告)日：2004-07-08

申请号：PCT/US0325269

申请日：2003-08-11

Applicant: ATMEL CORP

Inventor： TELECCO NICOLA

IPC: G11C11/419 ,  G11C7/06 ,  G01R19/00 ,  G11C7/00

CPC classification number: G11C7/067 ,  G11C7/065 ,  G11C7/08 ,  G11C2207/065

Abstract: A sense amplifier (15) that is configurable to operate in two modes in order to control a voltage swing on the sense amplifier output (40). The sense amplifier has two feedback paths (45 to 35) including a first feedback path (P101, N101, N133) having a transistor (N133) with a fast response time in order to allow the circuit to operate as fast as possible, and a second feedback path (P121, P102, N102, N121, N132, N131) for providing voltage swing control. In the first operating mode, the "turbo" mode, both feedback paths are in operation (BOOST = HIGH) to provide a higher margin of swing control, thus higher sensing speed. In the second operating mode, the "non-turbo" mode, only the first feedback path is in operation (BOOST = LOW) which allows for greater stability and a reduction in power consumption.

Abstract translation: 感测放大器（15）可被配置为以两种模式操作以控制感测放大器输出（40）上的电压摆动。 读出放大器具有两个反馈路径（45至35），包括具有快速响应时间的晶体管（N133）的第一反馈路径（P101，N101，N133），以允许电路尽可能快地工作， 第二反馈路径（P121，P102，N102，N121，N132，N131），用于提供电压摆动控制。 在第一种运行模式中，“涡轮”模式下，两个反馈路径都处于运行状态（BOOST = HIGH），以提供更高的回转控制余量，从而提高感测速度。 在第二种工作模式中，“非涡轮”模式下，只有第一个反馈路径处于工作状态（BOOST =低电平），这可以提供更高的稳定性并降低功耗。

公开(公告)号：WO2004003925A2

公开(公告)日：2004-01-08

申请号：PCT/US0314261

申请日：2003-05-01

Applicant: MOTOROLA INC

Inventor： NAHAS JOSEPH J ,  ANDRE THOMAS W ,  GARNI BRADLEY J ,  SUBRAMANIAN CHITRA K

IPC: G11C7/06 ,  G11C7/14 ,  G11C11/14 ,  G11C11/16

CPC classification number: G11C11/14 ,  G11C7/067 ,  G11C7/14 ,  G11C2207/063

Abstract: In a memory (10), a sensing system (14) detects bit states using one data (54) and two reference (64, 75) inputs, to sense a difference in conductance of a selected memory bit cell (77) and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell (78) in the high conductance state and a memory cell (79) in the low conductance state. The data input (54) is coupled to the selected memory bit cell (77). The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages (90, 150, 110, 130) amplifies the sense amplifier output without injecting parasitic errors.

Abstract translation: 在存储器（10）中，感测系统（14）使用一个数据（54）和两个参考（64,75）输入来检测位状态，以感测所选择的存储位单元（77）的电导差和中点 参考电导。 产生参考电导作为高电导状态的存储单元（78）的平均电导和低电导状态的存储单元（79）。 数据输入（54）耦合到选择的存储位单元（77）。 两个参考输入分别以高和低电导存储器状态耦合到存储器单元。 读出放大器使用电流偏置或电压偏置来在位单元之间的预定电压范围内施加感测电压。 耦合到读出放大器的互补输出的电容由电路设计来平衡。 在一种形式中，两个参考输入是内部连接的。 几个增益级（90,150,110,130）中的一个放大了读出放大器输出而不会注入寄生错误。

公开(公告)号：WO02078001A3

公开(公告)日：2002-11-07

申请号：PCT/US0208202

申请日：2002-03-13

Applicant: MATRIX SEMICONDUCTOR INC

Inventor： SCHEUERLEIN ROY E

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C8/08 ,  G11C8/10 ,  G11C17/18

CPC classification number: G11C8/10 ,  G11C5/025 ,  G11C7/062 ,  G11C7/067 ,  G11C7/18 ,  G11C8/08 ,  G11C17/18 ,  G11C2207/063

Abstract: The preferred embodiments described herein provide a memory device with row (55) and column (30) decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays (1-9). In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Abstract translation: 在此描述的优选实施例提供具有在多个存储器阵列（1-9）下以棋盘图案布置的行（55）和列（30）解码器电路的存储器装置。 在一个优选实施例中，存储器装置具有在多个存储器阵列下以棋盘图案排列的其行解码器电路和列解码器电路。 由于行解码器和列解码器电路中的每一个与其位置上方的存储器阵列以及相邻阵列相关联，因此与先前的方法相比提供了更密集的支持电路布置。 提供了其他优选实施例，并且本文所述的每个优选实施例可以单独使用或彼此组合使用。