Abstract:
Certain aspects of the present disclosure relate to methods and apparatus for wireless communication. More particularly, aspects of the present disclosure generally relate to techniques for wireless communications by an apparatus comprising a processing system configured to a processing system configured to generate a frame having at least a first header that is phase modulated and to modulate an amplitude of the first header prior to the first header being amplified by a power amplifier, and a first interface configured to output the frame for transmission.
Abstract:
Systems and methods are disclosed for using a monitoring application to measure channel state information during idle cycles in a mission-critical application. A first wireless communication device determines whether there is a mission-critical data packet to be transmitted to a second wireless communication device. If not, the first wireless communication device determines whether a monitoring packet should be transmitted to the second wireless communication device. If the first wireless communication device determines a monitoring packet should be sent, the first wireless communication devices transmits a monitoring packet containing an identifier and a reference signal to the second wireless communication device.
Abstract:
Techniques for indicating and determining a subframe timing of an access point on a shared communication medium are disclosed. A method of transmitting a discovery reference signal (DRS) may include establishing a transmission timing for transmission of the DRS relative to a system timing of an access point, determining whether to transmit the DRS during a particular SF based on the selected DRS transmission window, and transmitting the DRS to at least one access terminal during the particular SF in response to a determination to transmit the DRS.
Abstract:
A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.
Abstract:
Methods and apparatus supporting multiple concurrent service contexts sharing a single connectivity context are disclosed. A device may initiate a radio link with a network node and establish a connectivity context with the network node over the radio link using a connectivity logical context of the device. The network node may receive, authenticate, and authorize context establishment requests. A first service context with a first service management entity may be established over the radio link using a first logical context of the device, where the first logical context is distinct from the connectivity logical context. Multiple service connections using multiple service contexts based on multiple logical contexts of the device may share the connectivity context and may be established over the radio link.
Abstract:
Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB), compares the MSB to a receiver base address maintained in a shadow register, compares the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register, and sends the datagram to the receiver via the bus interface when: the MSB is equal to the receiver base address maintained in the shadow register, and the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.
Abstract:
An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.
Abstract:
A method of wireless communication by a user equipment includes determining an allocation of a set of tones in a symbol for conveying data. The method further includes determining to use m-ary phase shift keying (MPSK) to modulate the data onto a subset of tones of the set of tones. The method further includes modulating the data onto the subset of tones based on a mapping, wherein the mapping maps pairs of data values with a largest Hamming distance from each other to pairs of constellation points with a maximum Euclidean distance from each other.
Abstract:
Techniques for synchronization on a shared communication medium are disclosed. An access point may select, for example, a common sequence, frequency, and time for a first synchronization signal that is coordinated with one or more other access points. The access point may then transmit the first synchronization signal in accordance with the common sequence, frequency, and time. An access terminal may receive, from an access point, a first synchronization signal having a first sequence and a second synchronization signal having a second sequence. The access terminal may then determine an offset in time between the first synchronization signal and the second synchronization signal, and determine a cell identifier group associated with the access point based on the offset.
Abstract:
Certain aspects of the present disclosure provide methods and apparatus for implementing a fully differential charge pump circuit that eliminates a source of noise and power consumption by using a low-noise switched-capacitor common-mode feedback (CMFB) circuit, rather than a continuous-time amplifier-based CMFB circuit. The fully differential charge pump circuit presented in this disclosure includes the switched-capacitor CMFB (SC-CMFB) unit connected to differential output nodes of the charge pump and provides a feedback signal to the charge pump to control a common-mode voltage of the differential signals based on a reference common-mode voltage. In certain aspects, a replica phase-frequency detector (PFD), a frequency divider, and a non-overlapping clock generator provides control signals for the SCCMFB circuit.