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    GRADED SEMICONDUCTOR LAYER
    5.
    发明申请
    GRADED SEMICONDUCTOR LAYER 审中-公开
    分级半导体层

    公开(公告)号：WO2006023492A1

    公开(公告)日：2006-03-02

    申请号：PCT/US2005/029113

    申请日：2005-08-08

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  SADAKA, Mariam G. ,  THOMAS, Shawn G. ,  WHITE, Ted R. ,  LIU, Chun-Li ,  BARR, Alexander L. ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew

    Inventor： SADAKA, Mariam G. ,  THOMAS, Shawn G. ,  WHITE, Ted R. ,  LIU, Chun-Li ,  BARR, Alexander L. ,  NGUYEN, Bich-Yen ,  THEAN, Voon-Yew

    IPC: H01L21/84

    CPC classification number: H01L29/78687 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66742

    Abstract: A process for forming a semiconductor device. The process includes forming a template layer (207) for forming a layer (305) of strained silicon. In one example a layer (107) of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

    Abstract translation: 一种形成半导体器件的方法。 该方法包括形成用于形成应变硅层（305）的模板层（207）。 在一个示例中，形成梯度硅锗的层（107），其中锗在下部具有较高的浓度，在顶部处的浓度较低。 当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。 由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

    INTERFACIAL LAYER FOR USE WITH HIGH K DIELECTRIC MATERIALS
    6.
    发明申请
    INTERFACIAL LAYER FOR USE WITH HIGH K DIELECTRIC MATERIALS 审中-公开
    用于高K介电材料的界面层

    公开(公告)号：WO2006023027A1

    公开(公告)日：2006-03-02

    申请号：PCT/US2005/021498

    申请日：2005-06-16

    Applicant: FREESCALE SEMICONDUCTOR, INC. ,  THOMAS, Shawn, G. ,  MANIAR, Papu, D. ,  ILDEREM, Vida

    Inventor： THOMAS, Shawn, G. ,  MANIAR, Papu, D. ,  ILDEREM, Vida

    IPC: H01L21/00

    CPC classification number: H01L21/022 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/02664 ,  H01L21/28255 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus are provided for depositing a layer of pure germanium (12) can on a silicon substrate (11). This germanium layer is very thin, on the order of about 14 A, and is less than the critical thickness for pure germanium on silicon. The germanium layer (12) serves as an intermediate layer between the silicon substrate (11) and the high k gate layer (13), which is deposited on the germanium layer (12). The germanium layer (12) helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without: the drawbacks of series capacitance due to oxide impurities. The germanium layer (12) further improves mobility.

    Abstract translation: 提供了用于在硅衬底（11）上沉积纯锗（12）罐的层的方法和装置。 该锗层非常薄，约为14A，并且小于硅上的纯锗的临界厚度。 锗层（12）用作沉积在锗层（12）上的硅衬底（11）和高k栅极层（13）之间的中间层。 锗层（12）有助于在施加高k材料期间避免氧化物界面层的发展。 锗中间层在半导体结构中的应用导致高k栅极功能，而没有：由于氧化物杂质引起的串联电容的缺点。 锗层（12）进一步提高了移动性。

    A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR
    7.
    发明申请
    A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR 审中-公开
    一种制造硅绝缘体的方法

    公开(公告)号：WO2016196011A1

    公开(公告)日：2016-12-08

    申请号：PCT/US2016/033097

    申请日：2016-05-18

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  THOMAS, Shawn G.

    Inventor： THOMAS, Shawn G. ,  WANG, Gang

    IPC: H01L21/762 ,  H01L21/02

    CPC classification number: H01L21/76251 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3065

    Abstract: The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.

    Abstract translation: 所公开的方法适用于制造绝缘体上的SiGe结构。 根据该方法的一些实施例，包括SiGe的层被沉积在包括超薄硅顶层的绝缘体上的衬底上。 在一些实施例中，通过外延沉积沉积包含SiGe的层。 在一些实施例中，SiGe外延层是高质量的，因为其通过在Si /掩埋氧化物界面处工程化应变松弛而产生。 在一些实施方案中，该方法实现了在与下划线氧化物弱结合的少量单层厚Si层上生长的SiGe的弹性应变弛豫。

    METHOD OF MANUFACTURING HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE
    8.
    发明申请
    METHOD OF MANUFACTURING HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE 审中-公开
    制造高电阻绝缘子基板的方法

    公开(公告)号：WO2016036792A1

    公开(公告)日：2016-03-10

    申请号：PCT/US2015/048041

    申请日：2015-09-02

    Applicant: SUNEDISON SEMICONDUCTOR LIMITED ,  THOMAS, Shawn G.

    Inventor： THOMAS, Shawn G. ,  LIU, Qingmin

    IPC: H01L21/762

    CPC classification number: H01L29/66833 ,  H01L21/283 ,  H01L21/304 ,  H01L21/31 ,  H01L21/324 ,  H01L21/76254 ,  H01L29/0649 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a silicon dioxide layer on the surface of the semiconductor handle substrate; a carbon-doped amorphous silicon layer in contact with the silicon dioxide layer; a dielectric layer in contact with the carbon-doped amorphous silicon layer; and a semiconductor device layer in contact with the dielectric layer.

    Abstract translation: 提供了一种多层复合结构体及其制备方法。 多层复合结构包括具有至少约500欧姆 - 厘米的最小体积电阻率的半导体处理衬底; 在半导体手柄基板的表面上的二氧化硅层; 与二氧化硅层接触的碳掺杂非晶硅层; 与所述碳掺杂非晶硅层接触的介电层; 以及与电介质层接触的半导体器件层。

    ONE DIMENSIONAL NANOSTRUCTURE SPIRAL INDUCTORS
    9.
    发明申请
    ONE DIMENSIONAL NANOSTRUCTURE SPIRAL INDUCTORS 审中-公开
    一维纳米结构螺旋电感器

    公开(公告)号：WO2007067838A3

    公开(公告)日：2007-12-21

    申请号：PCT/US2006060936

    申请日：2006-11-15

    Applicant: MOTOROLA INC ,  THOMAS SHAWN G ,  ILDEREM VIDA ,  MANIAR PAPU D ,  MARACAS GEORGE N

    Inventor： THOMAS SHAWN G ,  ILDEREM VIDA ,  MANIAR PAPU D ,  MARACAS GEORGE N

    IPC: G06K19/06 ,  G08B13/14

    CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A method is provided for making an inductor comprising forming a catalytic material (14) over a substrate (12); and creating a network of one dimensional nanostructures (30) on the catalytic material, the network providing an inductance when a voltage is applied thereacross. This inductor is described in three applications: as an on-chip inductor for electronic circuitry, as a magnetic sensor, and as an environmental sensor. Several embodiments are described herein for forming networks of nanostructures on or above the substrate that provide an inductance having a high Q and a reduced die size for RF circuits. Several embodiments are also described for use of the nanostructure to sense gasses, radiation, a magnetic field, and the like.

    Abstract translation: 提供了一种用于制造电感器的方法，包括在衬底（12）上形成催化材料（14）; 以及在所述催化材料上形成一维纳米结构（30）的网络，所述网络在施加电压时提供电感。 该电感器在三个应用中被描述：作为用于电子电路的片上电感器，作为磁传感器，以及作为环境传感器。 本文描述了几个实施例，用于在衬底上或上方形成纳米结构网络，其提供具有高Q值的电感和用于RF电路的减小的管芯尺寸。 还描述了使用纳米结构来感测气体，辐射，磁场等的几个实施例。

    ONE DIMENSIONAL NANOSTRUCTURE SPIRAL INDUCTORS
    10.
    发明申请
    ONE DIMENSIONAL NANOSTRUCTURE SPIRAL INDUCTORS 审中-公开
    一维纳米结构螺旋电感

    公开(公告)号：WO2007067838A2

    公开(公告)日：2007-06-14

    申请号：PCT/US2006/060936

    申请日：2006-11-15

    Applicant: MOTOROLA INC. ,  THOMAS, Shawn, G. ,  ILDEREM, Vida ,  MANIAR, Papu, D. ,  MARACAS, George, N.

    Inventor： THOMAS, Shawn, G. ,  ILDEREM, Vida ,  MANIAR, Papu, D. ,  MARACAS, George, N.

    IPC: H01L21/64

    CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A method is provided for making an inductor comprising forming a catalytic material (14) over a substrate (12); and creating a network of one dimensional nanostructures (30) on the catalytic material, the network providing an inductance when a voltage is applied thereacross. This inductor is described in three applications: as an on-chip inductor for electronic circuitry, as a magnetic sensor, and as an environmental sensor. Several embodiments are described herein for forming networks of nanostructures on or above the substrate that provide an inductance having a high Q and a reduced die size for RF circuits. Several embodiments are also described for use of the nanostructure to sense gasses, radiation, a magnetic field, and the like.

    Abstract translation: 提供了一种用于制造电感器的方法，该方法包括在衬底（12）上形成催化材料（14）; 以及在催化材料上形成一维纳米结构（30）的网络，该网络在其上施加电压时提供电感。 该电感器在三个应用中有所描述：作为电子电路的片上电感器，磁性传感器和环境传感器。 本文描述了用于在衬底上或上方形成纳米结构网络的若干实施例，其为RF电路提供具有高Q值和减小的裸片尺寸的电感。 还描述了使用纳米结构来感测气体，辐射，磁场等的几个实施例。

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