公开(公告)号：WO2012009477A1

公开(公告)日：2012-01-19

申请号：PCT/US2011/043915

申请日：2011-07-13

Applicant: QUALCOMM INCORPORATED ,  BANERJEE, Gaurab ,  BEHERA, Manas ,  BARNETT, Kenneth Charles

Inventor： BANERJEE, Gaurab ,  BEHERA, Manas ,  BARNETT, Kenneth Charles

IPC: G06F11/27 ,  G01R31/3187

CPC classification number: G01R31/3187 ,  G06F11/27

Abstract: A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.

Abstract translation: 描述了内置的自检（BiST）系统。 BiST系统包括一个电路不足测试。 BiST系统还包括一个或多个嵌入式传感器。 每个嵌入式传感器包括连接到被测电路中的一个或多个节点的一个或多个开关。 BiST系统还包括信号发生器。 BiST系统还包括总线接口。 总线接口提供BiST系统的外部访问。

公开(公告)号：WO2011140563A1

公开(公告)日：2011-11-10

申请号：PCT/US2011/035791

申请日：2011-05-09

Applicant: QUALCOMM INCORPORATED ,  BANERJEE, Gaurab ,  BEHERA, Manas

Inventor： BANERJEE, Gaurab ,  BEHERA, Manas

IPC: G01R31/3167 ,  G01R31/28 ,  H03M1/10

CPC classification number: G01R31/3167 ,  G01R31/2843

Abstract: An integrated circuit with Built-in Self Test (BiST) is described. The integrated circuit includes a signal generator used to perform a BiST on the integrated circuit. The integrated circuit also includes a local oscillator used by the signal generator to generate one or more test signals used to perform the BiST on the integrated circuit.

Abstract translation: 描述了具有内置自检（BiST）的集成电路。 集成电路包括用于在集成电路上执行BiST的信号发生器。 集成电路还包括由信号发生器使用的本地振荡器，以产生用于在集成电路上执行BiST的一个或多个测试信号。

公开(公告)号：WO2007089885A2

公开(公告)日：2007-08-09

申请号：PCT/US2007/002722

申请日：2007-01-31

Applicant: INTEL CORPORATION ,  BANERJEE, Gaurab ,  MOONEY, Stephen

Inventor： BANERJEE, Gaurab ,  MOONEY, Stephen

IPC: H05K1/02 ,  H05K1/14 ,  H01L23/66 ,  H01P5/02

CPC classification number: H05K1/025 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09736 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: In some embodiments a passive impedance equalization network for high speed serial links is described. The impedance equalization network includes at least one stepped impedance transformer near points of impedance discontinuities. The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.

Abstract translation: 在一些实施例中，描述了用于高速串行链路的无源阻抗均衡网络。 阻抗均衡网络包括阻抗不连续点附近的至少一个阶梯式阻抗变压器。 阻抗不连续性可能在两个电路板之间的接口连接处。 电路板上的阻抗不连续性可能在管芯封装接口和/或封装板接口处。 阶梯式阻抗变压器可以形成为封装迹线，板迹线或两者。 在走线中形成阶梯式阻抗变压器不需要修改现有的封装/电路板设计方法或技术。 阶梯式阻抗变压器可以在一定频率范围内提供阻抗匹配。 为了解决在阶梯式阻抗变压器的设计中的建模误差，通过串行链路传输数据的集成电路可能包括用于选择发射机/接收机的输出/输入阻抗的有源电路。 其他实施例在此另外公开。

公开(公告)号：WO2007089885A3

公开(公告)日：2007-11-15

申请号：PCT/US2007002722

申请日：2007-01-30

Applicant: INTEL CORP ,  BANERJEE GAURAB ,  MOONEY STEPHEN

Inventor： BANERJEE GAURAB ,  MOONEY STEPHEN

IPC: H05K1/02 ,  H01L23/66 ,  H01P5/02 ,  H05K1/14

CPC classification number: H05K1/025 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09736 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A passive impedance equalization network (250,255,260,265) for high speed serial links is described. The impedance equalization network may include at least one stepped impedance transformer near points of impedance discontinuities (205,225,210,230). The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.

Abstract translation: 描述了用于高速串行链路的无源阻抗均衡网络（250,255,260,265）。 阻抗均衡网络可以包括在阻抗不连续点附近的至少一个阶梯式阻抗变压器（205,225,210,230）。 阻抗不连续性可能在两个电路板之间的接口连接处。 电路板上的阻抗不连续性可能在管芯封装接口和/或封装板接口处。 阶梯式阻抗变压器可以形成为封装迹线，板迹线或两者。 在走线中形成阶梯式阻抗变压器不需要修改现有的封装/电路板设计方法或技术。 阶梯式阻抗变压器可以在一定频率范围内提供阻抗匹配。 为了解决在阶梯式阻抗变压器的设计中的建模误差，通过串行链路传输数据的集成电路可能包括用于选择发射机/接收机的输出/输入阻抗的有源电路。 其他实施例在此另外公开。