公开(公告)号：WO2007089885A2

公开(公告)日：2007-08-09

申请号：PCT/US2007/002722

申请日：2007-01-31

Applicant: INTEL CORPORATION ,  BANERJEE, Gaurab ,  MOONEY, Stephen

Inventor： BANERJEE, Gaurab ,  MOONEY, Stephen

IPC: H05K1/02 ,  H05K1/14 ,  H01L23/66 ,  H01P5/02

CPC classification number: H05K1/025 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09736 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: In some embodiments a passive impedance equalization network for high speed serial links is described. The impedance equalization network includes at least one stepped impedance transformer near points of impedance discontinuities. The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.

Abstract translation: 在一些实施例中，描述了用于高速串行链路的无源阻抗均衡网络。 阻抗均衡网络包括阻抗不连续点附近的至少一个阶梯式阻抗变压器。 阻抗不连续性可能在两个电路板之间的接口连接处。 电路板上的阻抗不连续性可能在管芯封装接口和/或封装板接口处。 阶梯式阻抗变压器可以形成为封装迹线，板迹线或两者。 在走线中形成阶梯式阻抗变压器不需要修改现有的封装/电路板设计方法或技术。 阶梯式阻抗变压器可以在一定频率范围内提供阻抗匹配。 为了解决在阶梯式阻抗变压器的设计中的建模误差，通过串行链路传输数据的集成电路可能包括用于选择发射机/接收机的输出/输入阻抗的有源电路。 其他实施例在此另外公开。

公开(公告)号：WO2005027446A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/029175

申请日：2004-09-08

Applicant: INTEL CORPORATION ,  BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

Inventor： BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

IPC: H04L25/03

CPC classification number: H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: (I), where (II) is the filter vector representing the filter taps of the FIR filter, (III) is the data vector representing present and past samples of the received data x (t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K .

Abstract translation: 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：（I），其中（II）是表示 FIR滤波器的滤波器抽头（III）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是 FIR滤波器，μ确定适配的存储器或窗口大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。 此外，提供了用于校准比例因子K的过程和电路结构。

公开(公告)号：WO2005109148A1

公开(公告)日：2005-11-17

申请号：PCT/US2005/012075

申请日：2005-04-08

Applicant: INTEL CORPORATION ,  KENNEDY, Joseph ,  MOONEY, Stephen

Inventor： KENNEDY, Joseph ,  MOONEY, Stephen

IPC: G06F1/10

CPC classification number: H03L7/0812

Abstract: A chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal.

Abstract translation: 一个芯片包括一个芯片接口，用于接受来自芯片外部的延迟控制信号。 芯片还包括可控延迟线，以响应于延迟控制信号来延迟输入信号，以提供具有与输入信号的特定相位关系的输出信号。

公开(公告)号：WO2012078632A1

公开(公告)日：2012-06-14

申请号：PCT/US2011/063531

申请日：2011-12-06

Applicant: LOCKERZ, INC. ,  DESTEIN, Bill ,  BORTNIK, Michal ,  ZHU, Qinchao ,  MOONEY, Stephen

Inventor： DESTEIN, Bill ,  BORTNIK, Michal ,  ZHU, Qinchao ,  MOONEY, Stephen

IPC: G06Q30/00

CPC classification number: G06Q30/0276

Abstract: A system and method for creating shareable Internet-based advertisements includes administration console receiving data for Internet-based advertisement from a client, configuring an overlay to provide on top of the Internet-based advertisement. A database operatively connected to the administration console stores data and code related to overlay and advertisement. A share tag is applied to the advertisement, the share tag including a script reference pointing to the stored data and code stored in database. A share tag server retrieves the stored data and code and displays the overlay on the advertisement as an expanded share tag, upon activation of the share tag of the advertisement published on a content website. Upon activation of a share feature on the expanded share tag, the share tag server provides, to a desired social media network server, the stored data needed to display the advertisement on the user's social media network page.

Abstract translation: 用于创建可共享的基于因特网的广告的系统和方法包括管理控制台从客户端接收基于因特网的广告的数据，配置覆盖以在基于因特网的广告之上提供。 可操作地连接到管理控制台的数据库存储与覆盖和广告相关的数据和代码。 共享标签被应用于广告，共享标签包括指向存储的数据的脚本引用和存储在数据库中的代码。 共享标签服务器在激活内容网站上发布的广告的共享标签时，检索存储的数据和代码，并将广告上的叠加层显示为扩展的共享标签。 在激活扩展的共享标签上的共享功能之后，共享标签服务器向期望的社交媒体网络服务器提供在用户的社交媒体网络页面上显示广告所需的所存储的数据。

公开(公告)号：WO2002084877A2

公开(公告)日：2002-10-24

申请号：PCT/US2002/009846

申请日：2002-03-29

Applicant: INTEL CORPORATION

Inventor： MOONEY, Stephen ,  MARTIN, Aaron

IPC: H03K19/0185

CPC classification number: H04L25/0282 ,  H03K19/01721 ,  H03K19/018528 ,  H04L25/0272 ,  H04L25/0294

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract translation: 电流模式驱动器包括尾电流器件，差分输入晶体管对，共源共栅输出晶体管和预充电电路，用于对差分输入晶体管对和共源共栅输出晶体管之间的共源共栅节点进行充电。 电流模式驱动器由CMOS驱动器驱动，交替地将输入晶体管打开和关闭。 宽摆幅偏置电路为电流模式驱动器提供偏置电压。 尾电流器件的偏置电压紧密匹配，以提供偏置电路和电流模式驱动器之间的电流匹配。

公开(公告)号：WO2002084877A3

公开(公告)日：2002-10-24

申请号：PCT/US2002/009846

申请日：2002-03-29

Applicant: INTEL CORPORATION

Inventor： MOONEY, Stephen ,  MARTIN, Aaron

IPC: H03K19/0185

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, (104, 106) cascode output transistors, (112, 114) and pre-charge circuits (108, 110) to charge cascode nodes (109, 111) between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

公开(公告)号：WO2005027445A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/029055

申请日：2004-09-03

Applicant: INTEL CORPORATION

Inventor： BALAMURUGAN, Ganesh ,  CASPER, Bryan ,  JAUSSI, James ,  MOONEY, Stephen

IPC: H04L25/03

CPC classification number: H04L25/03038 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L2025/03477

Abstract: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h ( t + 1) = h ( t ) + µ [sgn { d ( t )} - sgn { z ( t ) - Kd ( t )}]sgn {x( t )} , where h ( t ) is the filter vector representing the filter taps of the FIR filter, x( t ) is the data vector representing present and past samples of the received data x ( t ), d ( t ) is the desired data used for training, z ( t ) is the output of the FIR filter, µ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

Abstract translation: 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：h（t + 1）= h（t）+μ [sgn {d（t）} - sgn {z（t）-Kd（t）}] sgn {x（t）}，其中h（t）是表示FIR滤波器的滤波器抽头的滤波器向量， t）是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，μ确定存储器或窗口 适应的大小，K是考虑通信信道，接收机和均衡器的实际限制的比例因子。 此外，提供了用于校准比例因子K的过程和电路结构。

公开(公告)号：WO2004100357A2

公开(公告)日：2004-11-18

申请号：PCT/US2004/008921

申请日：2004-03-24

Applicant: INTEL CORPORATION

Inventor： JAUSSI, James ,  KENNEDY, Joseph ,  MOONEY, Stephen

IPC: H03F3/45

CPC classification number: H03F1/486 ,  H03F3/4521 ,  H03F2200/36 ,  H03K19/01759 ,  H03K19/018592

Abstract: An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.

Abstract translation: 放大器包括多个阶段。 多级放大器的早期阶段具有较低的增益并保持带宽。