公开(公告)号：WO2013115816A1

公开(公告)日：2013-08-08

申请号：PCT/US2012/023597

申请日：2012-02-02

Applicant: INTEL CORPORATION ,  DIXON, Martin, G. ,  RAJWAR, Ravi ,  LAI, Konrad K. ,  CHAPPELL, Robert, S. ,  PARTHASARATHY, Rajesh, S. ,  FARCY, Alexandre, J. ,  KIM, Ilhyun ,  MATH, Prakash ,  MERTEN, Matthew ,  KADGI, Vijaykumar

Inventor： DIXON, Martin, G. ,  RAJWAR, Ravi ,  LAI, Konrad K. ,  CHAPPELL, Robert, S. ,  PARTHASARATHY, Rajesh, S. ,  FARCY, Alexandre, J. ,  KIM, Ilhyun ,  MATH, Prakash ,  MERTEN, Matthew ,  KADGI, Vijaykumar

IPC: G06F1/00 ,  G06F9/30 ,  G06F9/305 ,  G06F13/14

CPC classification number: G06F9/3855 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/1045 ,  G06F13/1673 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/682

Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

Abstract translation: 本文描述了一种用于提供鲁棒的推测代码部分中止控制机制的装置和方法。 硬件能够跟踪推测性代码区域中止事件，条件和/或场景，例如显式中止指令，数据冲突，推测定时器到期，不允许的指令属性或类型等。硬件，固件，软件， 或其组合基于跟踪的中止事件进行中止判定。 作为示例，硬件可以基于一个或多个预定义事件进行初始中止确定，或者选择将事件信息传递到固件或软件处理程序以进行这种中止确定。 在确定要执行推测代码区域的中止时，硬件，固件，软件或其组合执行中止，其可以包括跟随由硬件或软件指定的回退路径。 并且为了能够测试这样的回退路径，在一个实现中，硬件为软件提供一种总是中止推测代码区域的机制。

公开(公告)号：WO2012040425A2

公开(公告)日：2012-03-29

申请号：PCT/US2011052696

申请日：2011-09-22

Applicant: INTEL CORP ,  BAIR MICHAEL S ,  ONG LESLIE A ,  TUCKNOTT MICHAEL D ,  BURNS DAVID W ,  RAGHUVANSHI PANKAJ ,  YANOVER IGOR ,  CHAPPELL ROBERT S ,  RAIKIN SHLOMO ,  MATH PRAKASH ,  SADE RAANAN

Inventor： BAIR MICHAEL S ,  ONG LESLIE A ,  TUCKNOTT MICHAEL D ,  BURNS DAVID W ,  RAGHUVANSHI PANKAJ ,  YANOVER IGOR ,  CHAPPELL ROBERT S ,  RAIKIN SHLOMO ,  MATH PRAKASH ,  SADE RAANAN

IPC: G06F15/76 ,  G06F12/00 ,  G06F13/14

CPC classification number: G06F9/526

Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，将定时器与第一线程相关联，并且在完成第一线程之后阻止第一线程执行存储器群集操作 原子内存操作，直到预防窗口过去。 在一些实施例中，该方法可以由与处理器的存储器执行单元相关联的调节逻辑来执行。 描述并要求保护其他实施例。

公开(公告)号：WO2014105151A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046910

申请日：2013-06-20

Applicant: INTEL CORPORATION ,  RAIKIN, Shlomo ,  HAMAMA, Oren ,  CHAPPELL, Robert S. ,  RUST, Camron B. ,  LUU, Han S. ,  ONG, Leslie A. ,  HILDESHEIM, Gur

Inventor： RAIKIN, Shlomo ,  HAMAMA, Oren ,  CHAPPELL, Robert S. ,  RUST, Camron B. ,  LUU, Han S. ,  ONG, Leslie A. ,  HILDESHEIM, Gur

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/652 ,  Y02D10/13

Abstract: An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.

Abstract translation: 一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。 例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

公开(公告)号：WO2013095576A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067036

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  WOLRICH, Gilbert M. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi K. ,  YAP, Kirk S. ,  GULLEY, Sean M. ,  DIXON, Martin G. ,  CHAPPELL, Robert S.

Inventor： GOPAL, Vinodh ,  GUILFORD, James D. ,  WOLRICH, Gilbert M. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi K. ,  YAP, Kirk S. ,  GULLEY, Sean M. ,  DIXON, Martin G. ,  CHAPPELL, Robert S.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/34

Abstract: An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.

Abstract translation: 描述了一种用于使用面向位的指令来处理比特流的装置和方法。 例如，根据一个实施例的方法包括以下操作：执行用于获得用于操作的比特的指令，所述指令标识起始比特地址和要检索的比特数; 从面向比特的寄存器或高速缓存中检索由起始位地址和位数标识的位; 并对所检索的位执行指定位操作的序列以产生结果。

公开(公告)号：WO2013115818A1

公开(公告)日：2013-08-08

申请号：PCT/US2012/023611

申请日：2012-02-02

Applicant: INTEL CORPORATION ,  RAJWAR, Ravi ,  DIXON, Martin G. ,  LAI, Konrad K. ,  FARCY, Alexandre J. ,  TOLL, Bret L. ,  CHAPPELL, Robert S. ,  MERTEN, Matthew C. ,  PARTHASARATHY, Rajesh S. ,  HAMMARLUND, Per

Inventor： RAJWAR, Ravi ,  DIXON, Martin G. ,  LAI, Konrad K. ,  FARCY, Alexandre J. ,  TOLL, Bret L. ,  CHAPPELL, Robert S. ,  MERTEN, Matthew C. ,  PARTHASARATHY, Rajesh S. ,  HAMMARLUND, Per

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30181 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3859

Abstract: An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similary provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.

Abstract translation: 这里描述了一种用于提供猜测控制指令的装置和方法。 提供xAcquire和xRelease指令来定义关键部分。 在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。 因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。 但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。 此外，xBegin和xEnd在指令集架构（ISA）中提供了类似的方式来定义事务代码区域。 此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

公开(公告)号：WO2012040723A3

公开(公告)日：2012-06-21

申请号：PCT/US2011053306

申请日：2011-09-26

Applicant: INTEL CORP ,  HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

Inventor： HINTON GLENN ,  RAMANUJAN RAJ ,  CAPE SCOTT J ,  PARTHASARATHY MADHAVAN ,  ZIMMERMAN DAVID ,  DOWNER WAYNE A ,  PARTHASARATHY RAJESH ,  SMITH LARRY O ,  CHAPPELL ROBERT S ,  SWAMINATHAN MUTHUKUMAR ,  MOGA ADRIAN C

IPC: G06F12/00 ,  G06F9/06 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

Abstract translation: 公开了一种装置，方法，机器可读介质和系统。 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。 微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。 当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

公开(公告)号：WO2013115820A1

公开(公告)日：2013-08-08

申请号：PCT/US2012/023618

申请日：2012-02-02

Applicant: INTEL CORPORATION ,  RAJWAR, Ravi ,  DIXON, Martin, G. ,  LAI, Konrad K. ,  CHAPPELL, Robert, S. ,  TOLL, Bret, L.

Inventor： RAJWAR, Ravi ,  DIXON, Martin, G. ,  LAI, Konrad K. ,  CHAPPELL, Robert, S. ,  TOLL, Bret, L.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/467 ,  G06F12/0828

Abstract: An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to 'escape' a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.

Abstract translation: 这里描述了一种用于提供推测逃逸指令的装置和方法。 具体地，本文描述了显式的非事务性加载操作。 在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。 然而，编程器或编译器可以利用显式非事务读取将存储器地址加载到目标寄存器中，而不将读/加载加到事务读取集。 同样，也提供非事务存储。 这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。 并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。 换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。

公开(公告)号：WO2012040723A2

公开(公告)日：2012-03-29

申请号：PCT/US2011/053306

申请日：2011-09-26

Applicant: INTEL CORPORATION ,  HINTON, Glenn ,  RAMANUJAN, Raj ,  CAPE, Scott J. ,  PARTHASARATHY, Madhavan ,  ZIMMERMAN, David ,  DOWNER, Wayne A. ,  PARTHASARATHY, Rajesh ,  SMITH, Larry O. ,  CHAPPELL, Robert S. ,  SWAMINATHAN, Muthukumar ,  MOGA, Adrian C.

Inventor： HINTON, Glenn ,  RAMANUJAN, Raj ,  CAPE, Scott J. ,  PARTHASARATHY, Madhavan ,  ZIMMERMAN, David ,  DOWNER, Wayne A. ,  PARTHASARATHY, Rajesh ,  SMITH, Larry O. ,  CHAPPELL, Robert S. ,  SWAMINATHAN, Muthukumar ,  MOGA, Adrian C.

IPC: G06F12/00 ,  G06F9/06 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

Abstract translation: 公开了一种装置，方法，机器可读介质和系统。 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页的存储器页请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的转换后备缓冲器（TLB）。 另外，该装置还具有能够响应于TLB未存储由存储器页面请求所引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表格中执行微物理地址查找的页面未命中处理器。 该装置还包括能够管理页面未命中处理器标签表项的存储器管理逻辑。 微页表引擎允许TLB成为代理，用于确定两级存储器层级中的数据是处于内存的热区还是处于内存的寒冷区域。 当数据处于内存冷区时，微页表引擎将数据提取到热内存，然后将热内存块推送到冷内存区。

公开(公告)号：WO2012040425A3

公开(公告)日：2012-03-29

申请号：PCT/US2011/052696

申请日：2011-09-22

Applicant: INTEL CORPORATION ,  BAIR, Michael, S. ,  ONG, Leslie, A. ,  TUCKNOTT, Michael, D. ,  BURNS, David, W. ,  RAGHUVANSHI, Pankaj ,  YANOVER, Igor ,  CHAPPELL, Robert, S. ,  RAIKIN, Shlomo ,  MATH, Prakash ,  SADE, Raanan

Inventor： BAIR, Michael, S. ,  ONG, Leslie, A. ,  TUCKNOTT, Michael, D. ,  BURNS, David, W. ,  RAGHUVANSHI, Pankaj ,  YANOVER, Igor ,  CHAPPELL, Robert, S. ,  RAIKIN, Shlomo ,  MATH, Prakash ,  SADE, Raanan

IPC: G06F15/76 ,  G06F13/14 ,  G06F12/00

Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.