公开(公告)号：WO2012151520A3

公开(公告)日：2013-01-10

申请号：PCT/US2012036582

申请日：2012-05-04

Applicant: LIGHTWIRE LLC ,  SHASTRI KALPENDU ,  PATEL VIPULKUMAR ,  WEBSTER MARK ,  GOTHOSKAR PRAKASH ,  KACHRU RAVINDER ,  PATHAK SOHAM ,  YELAMARTY RAO V ,  DAUGHERTY THOMAS ,  DAMA BIPIN ,  PATEL KAUSHIK ,  DESAI KISHOR

Inventor： SHASTRI KALPENDU ,  PATEL VIPULKUMAR ,  WEBSTER MARK ,  GOTHOSKAR PRAKASH ,  KACHRU RAVINDER ,  PATHAK SOHAM ,  YELAMARTY RAO V ,  DAUGHERTY THOMAS ,  DAMA BIPIN ,  PATEL KAUSHIK ,  DESAI KISHOR

IPC: H01L25/16 ,  H01L25/18

CPC classification number: H01L25/50 ,  G02B6/423 ,  G02B6/4244 ,  G02B6/4245 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/426 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a "platform" (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

Abstract translation: 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义 分离光学元件之间的光信号路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片级组装过程以及这些模块的光学对准和测试。

公开(公告)号：WO2013071279A1

公开(公告)日：2013-05-16

申请号：PCT/US2012/064758

申请日：2012-11-13

Applicant: CISCO TECHNOLOGY, INC. ,  SHASTRI, Kalpendu ,  KACHRU, Ravinder ,  DESAI, Kishor

Inventor： SHASTRI, Kalpendu ,  KACHRU, Ravinder ,  DESAI, Kishor

IPC: G02B6/42

CPC classification number: G02B6/423 ,  G01B11/14 ,  G02B6/4239 ,  G02B6/4249

Abstract: An arrangement for providing passive alignment of optical components on a common substrate uses a set of reference cavities, where each optical device is positioned within a separate reference cavity. The reference cavities are formed to have a predetermined depth, with perimeters slightly larger than the footprint of their associated optical components. The reference cavity includes at least one right-angle corner that is used as a registration corner against which a right-angle corner of an associated optical component is positioned. The placement of each optical component in its own reference cavity allows for passive optical alignment to be achieved by placing each component against its predefined registration corner.

Abstract translation: 用于在公共衬底上提供光学部件的被动对准的装置使用一组参考腔，其中每个光学装置定位在单独的参考腔内。 参考空腔形成为具有预定深度，其周长稍大于其相关联的光学部件的覆盖区。 参考腔包括至少一个直角角，其被用作相关联的光学部件的直角角位于其上的配准角。 每个光学部件在其自己的参考腔中的放置允许通过将每个部件放置在其预定义的配准角上来实现无源光学对准。

公开(公告)号：WO2013059731A1

公开(公告)日：2013-04-25

申请号：PCT/US2012/061200

申请日：2012-10-19

Applicant: CISCO TECHNOLOGY, INC. ,  DESAI, Kishor ,  KACHRU, Ravinder ,  PATEL, Vipulkumar ,  DAMA, Bipin ,  SHASTRI, Kalpendu ,  PATHAK, Soham

Inventor： DESAI, Kishor ,  KACHRU, Ravinder ,  PATEL, Vipulkumar ,  DAMA, Bipin ,  SHASTRI, Kalpendu ,  PATHAK, Soham

IPC: G02B6/42 ,  H01L25/16

CPC classification number: G02B6/4255 ,  G02B6/12 ,  G02B6/13 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4292 ,  G02B6/43 ,  H01L21/50 ,  H01L23/04 ,  H01L23/48 ,  H01L25/167 ,  H01L31/0203 ,  H01L33/52 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1616 ,  H01L2924/165 ,  H01L2924/16788 ,  H05K1/0268 ,  H05K1/0274 ,  H05K2201/10121 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: An opto-electronic assembly is provided comprising a substrate 20 (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material 22 is disposed to outline a defined peripheral area of the substrate. A molded glass lid 10 is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.

Abstract translation: 提供了一种光电组件，其包括用于支撑多个互连的光学和电气部件的基底20（通常为硅或玻璃）。 设置密封材料层22以概述衬底的限定的周边区域。 模制玻璃盖10设置在基底上并结合到基底上，其中模制的玻璃盖被配置成产生与限定的基底周边区域匹配的覆盖区。 模制玻璃盖的底表面包括一层接合材料，其在接触时与基底的密封材料层接触，形成结合组件。 在一种形式中，提出了一种晶片级组装工艺，其中多个光电组件设置在硅晶片上，并且多个玻璃盖被模制在一片玻璃中，然后将其粘合到硅晶片上。

公开(公告)号：WO2012151520A2

公开(公告)日：2012-11-08

申请号：PCT/US2012/036582

申请日：2012-05-04

Applicant: LIGHTWIRE LLC ,  SHASTRI, Kalpendu ,  PATEL, Vipulkumar ,  WEBSTER, Mark ,  GOTHOSKAR, Prakash ,  KACHRU, Ravinder ,  PATHAK, Soham ,  YELAMARTY, Rao, V. ,  DAUGHERTY, Thomas ,  DAMA, Bipin ,  PATEL, Kaushik ,  DESAI, Kishor

Inventor： SHASTRI, Kalpendu ,  PATEL, Vipulkumar ,  WEBSTER, Mark ,  GOTHOSKAR, Prakash ,  KACHRU, Ravinder ,  PATHAK, Soham ,  YELAMARTY, Rao, V. ,  DAUGHERTY, Thomas ,  DAMA, Bipin ,  PATEL, Kaushik ,  DESAI, Kishor

IPC: H01L25/16 ,  H01L25/18

CPC classification number: H01L25/50 ,  G02B6/423 ,  G02B6/4244 ,  G02B6/4245 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/426 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a "platform" (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

Abstract translation: 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义 分离光学元件之间的光信号路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

公开(公告)号：WO1991014202A1

公开(公告)日：1991-09-19

申请号：PCT/US1990001345

申请日：1990-03-15

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION ,  KACHRU, Ravinder ,  XU, Emily, Y. ,  KROLL, Stefan ,  HUESTIS, David, L. ,  KIM, Myung-Keun

Inventor： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

IPC: G02F01/35

CPC classification number: G06K9/74 ,  G02F2/02 ,  G06E3/003

Abstract: An image processing apparatus having a third-order nonlinear stimulated photon echo medium (1). The photo echo medium (1) can store large numbers of images in the form of a Fourier transformed pattern by spectral modulation. The spectral modulation is carried out by sending optical pulses and an optical pulse train having (or not having) image information to the medium (1) so that the population in the ground and excited states are modulated after the passage of the pulse trains and pulses. The Fourier transformed pattern is converted back to temporal modulation, consisting of a sequence of echo pulses that reproduce the original data pulse train. By using the apparatus, ultrafast operation such as convolution and correlation between a number of reference images and a test image can be achieved.

Abstract translation: 一种具有三阶非线性受激光子回波介质（1）的图像处理装置。 光回波介质（1）可以通过光谱调制以傅里叶变换图案的形式存储大量的图像。 通过向介质（1）发送光脉冲和具有（或不具有）图像信息的光脉冲序列来执行频谱调制，使得在脉冲序列和脉冲通过之后调制地面和激发态的群体 。 傅里叶变换图案被转换回到时间调制，其由再现原始数据脉冲串的回波脉冲序列组成。 通过使用该装置，可以实现诸如卷积的超快速操作和多个参考图像与测试图像之间的相关性。