公开(公告)号：WO2012106332A1

公开(公告)日：2012-08-09

申请号：PCT/US2012/023316

申请日：2012-01-31

Applicant: EVERSPIN TECHNOLOGIES, INC. ,  ALAM, Syed M. ,  ANDRE, Thomas ,  CROFT, Matthew R. ,  SUBRAMANIAN, Chitra ,  LIN, Halbert

Inventor： ALAM, Syed M. ,  ANDRE, Thomas ,  CROFT, Matthew R. ,  SUBRAMANIAN, Chitra ,  LIN, Halbert

IPC: G11C11/00

CPC classification number: G11C11/1675 ,  G06F11/1048 ,  G06F11/1076 ,  G11C11/00 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0076 ,  G11C2029/0411

Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read.

Abstract translation: 一种方法包括破坏性地读取自旋扭矩磁随机存取存储器的位并立即写回原始值或反相值。 采用回写位的多数状态的检测和回写位的条件反转来减少回写脉冲的数量。 在指定时间内或在原始写入操作开始之前接收到的后续写入命令将导致回写脉冲的一部分或原始写入操作脉冲中止。 在后续写入操作期间的写入脉冲将遵循在破坏性读取期间为回写位确定的条件反演。

公开(公告)号：WO2005027135A1

公开(公告)日：2005-03-24

申请号：PCT/US2004/022510

申请日：2004-07-15

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  NAHAS, Joseph, J. ,  ANDRE, Thomas, W. ,  SUBRAMANIAN, Chitra, K. ,  LIN, Halbert

Inventor： NAHAS, Joseph, J. ,  ANDRE, Thomas, W. ,  SUBRAMANIAN, Chitra, K. ,  LIN, Halbert

IPC: G11C11/00

CPC classification number: G11C11/1695 ,  G11C11/1675

Abstract: A write driver (36) uses a reference current (102) that is reflected to a driver circuit (114) by a voltage. The driver circuit (114) is sized in relation to the device (104) that provides the voltage so that the current through the driver (114) is a predetermined multiple of the reference current (102). This voltage is coupled to the driver circuit (114) through a switch (110). The switch (110) is controlled so that the driver circuit (114) only receives the voltage when the write line (52) is to have write current through it as determined by a decoder (22) responsive to an address. The driver (114) is affirmatively disabled when the write line (52) is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled (120) to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.

Abstract translation: 写驱动器（36）使用被电压反射到驱动电路（114）的参考电流（102）。 驱动器电路（114）的尺寸相对于提供电压的装置（104）的尺寸，使得通过驱动器（114）的电流是参考电流（102）的预定倍数。 该电压通过开关（110）耦合到驱动器电路（114）。 控制开关（110）使得当写入线（52）响应于地址由解码器（22）确定时，驱动器电路（114）仅接收电压。 当写入线（52）旨在不具有通过它的电流时，驱动器（114）被肯定地禁用。 作为克服由于高电流引起的地面反弹的增强，驱动器的输入可以电容耦合（120）到经历这种反弹的接地端子。 附加的增强功能可以提供幅度和边缘速率控制的优点。

公开(公告)号：WO2014124271A1

公开(公告)日：2014-08-14

申请号：PCT/US2014/015319

申请日：2014-02-07

Applicant: SUBRAMANIAN, Chitra K. ,  LIN, Halbert S. ,  ALAM, Syed M. ,  ANDRE, Thomas ,  EVERSPIN TECHNOLOGIES, INC.

Inventor： SUBRAMANIAN, Chitra K. ,  LIN, Halbert S. ,  ALAM, Syed M. ,  ANDRE, Thomas

IPC: G06F11/00

CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements.

Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。

公开(公告)号：WO2014058994A3

公开(公告)日：2014-07-24

申请号：PCT/US2013064088

申请日：2013-10-09

Applicant: THOMAS ANDRE ,  ALAM SYED M ,  LIN HALBERT S ,  EVERSPIN TECHNOLOGIES INC

Inventor： ANDRE THOMAS ,  ALAM SYED M ,  LIN HALBERT S

IPC: G11C7/00 ,  G11C11/4076

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到预充电命令和响应于接收到激活命令的与激活命令有关的第二系列事件，存储器设备执行与预充电命令有关的第一系列事件。 存储设备延迟第二系列事件的开始，直到第一系列事件完成。

公开(公告)号：WO2014058994A2

公开(公告)日：2014-04-17

申请号：PCT/US2013/064088

申请日：2013-10-09

Applicant: ANDRE, Thomas ,  ALAM, Syed M. ,  LIN, Halbert S. ,  EVERSPIN TECHNOLOGIES, INC.

Inventor： ANDRE, Thomas ,  ALAM, Syed M. ,  LIN, Halbert S.

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。